NO

Initial ITS
Start location: l12
   0: l0 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post0, lt_14^0'=lt_14^post0, ct_15^0'=ct_15^post0, InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, cnt_29^0'=cnt_29^post0, lt_20^0'=lt_20^post0, lt_17^0'=lt_17^post0, __disjvr_0^0'=__disjvr_0^post0, Result_4^0'=Result_4^post0, lt_13^0'=lt_13^post0, ct_115^0'=ct_115^post0, lt_19^0'=lt_19^post0, Dc_6^0'=Dc_6^post0, __retres1_10^0'=__retres1_10^post0, __const_256^0'=__const_256^post0, lt_16^0'=lt_16^post0, ct_64^0'=ct_64^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, lt_12^0'=lt_12^post0, cnt_34^0'=cnt_34^post0, ntStatus_8^0'=ntStatus_8^post0, lt_18^0'=lt_18^post0, __disjvr_1^0'=__disjvr_1^post0, (0 == 0 /\ -lt_18^post0+lt_18^0 == 0 /\ __disjvr_0^0-__disjvr_0^post0 == 0 /\ lt_12^0-lt_12^post0 == 0 /\ -__disjvr_1^post0+__disjvr_1^0 == 0 /\ lt_13^0-lt_13^post0 == 0 /\ lt_17^0-lt_17^post0 == 0 /\ -cnt_34^post0+cnt_34^0 == 0 /\ lt_20^0-lt_20^post0 == 0 /\ -lt_19^post0+lt_19^0 == 0 /\ -Result_4^post0+Result_4^0 == 0 /\ -ct_64^post0+ct_64^0 == 0 /\ -__retres1_10^post0+__retres1_10^0 == 0 /\ lt_14^0-lt_14^post0 == 0 /\ ct_15^0-ct_15^post0 == 0 /\ lt_16^0-lt_16^post0 == 0 /\ cnt_29^0-cnt_29^post0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post0 == 0 /\ -__const_256^post0+__const_256^0 == 0 /\ -ct_115^post0+ct_115^0 == 0), cost: 1
   1: l1 -> l2 : __cil_tmp2_11^0'=__cil_tmp2_11^post1, lt_14^0'=lt_14^post1, ct_15^0'=ct_15^post1, InterfaceType_5^0'=InterfaceType_5^post1, fdoExtension_7^0'=fdoExtension_7^post1, cnt_29^0'=cnt_29^post1, lt_20^0'=lt_20^post1, lt_17^0'=lt_17^post1, __disjvr_0^0'=__disjvr_0^post1, Result_4^0'=Result_4^post1, lt_13^0'=lt_13^post1, ct_115^0'=ct_115^post1, lt_19^0'=lt_19^post1, Dc_6^0'=Dc_6^post1, __retres1_10^0'=__retres1_10^post1, __const_256^0'=__const_256^post1, lt_16^0'=lt_16^post1, ct_64^0'=ct_64^post1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post1, lt_12^0'=lt_12^post1, cnt_34^0'=cnt_34^post1, ntStatus_8^0'=ntStatus_8^post1, lt_18^0'=lt_18^post1, __disjvr_1^0'=__disjvr_1^post1, (0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post1 == 0 /\ lt_13^0-lt_13^post1 == 0 /\ -1+lt_16^10-cnt_29^0 == 0 /\ -ntStatus_8^post1+ntStatus_8^0 == 0 /\ 1+lt_16^10-lt_17^10 <= 0 /\ lt_17^10-cnt_34^0 == 0 /\ cnt_34^0-cnt_34^post1 == 0 /\ -lt_12^post1+lt_12^0 == 0 /\ -__retres1_10^post1+__retres1_10^0 == 0 /\ 1-lt_20^10+lt_19^10 <= 0 /\ lt_20^10-cnt_34^0 == 0 /\ -__const_256^post1+__const_256^0 == 0 /\ cnt_29^0-cnt_29^post1 == 0 /\ Dc_6^0-Dc_6^post1 == 0 /\ -cnt_29^0+lt_18^10 == 0 /\ -cnt_29^0+lt_19^10 == 0 /\ Result_4^0-Result_4^post1 == 0 /\ InterfaceType_5^0-InterfaceType_5^post1 == 0 /\ -ct_115^post1+ct_115^0 == 0 /\ ct_64^0-ct_64^post1 == 0 /\ -fdoExtension_7^post1+fdoExtension_7^0 == 0 /\ -ct_115^0+lt_14^10 == 0 /\ -__disjvr_1^post1+__disjvr_1^0 == 0 /\ -MaximumInterfaceType_9^post1+MaximumInterfaceType_9^0 == 0 /\ __disjvr_0^0-__disjvr_0^post1 == 0 /\ lt_14^10 <= 0), cost: 1
   3: l1 -> l3 : __cil_tmp2_11^0'=__cil_tmp2_11^post3, lt_14^0'=lt_14^post3, ct_15^0'=ct_15^post3, InterfaceType_5^0'=InterfaceType_5^post3, fdoExtension_7^0'=fdoExtension_7^post3, cnt_29^0'=cnt_29^post3, lt_20^0'=lt_20^post3, lt_17^0'=lt_17^post3, __disjvr_0^0'=__disjvr_0^post3, Result_4^0'=Result_4^post3, lt_13^0'=lt_13^post3, ct_115^0'=ct_115^post3, lt_19^0'=lt_19^post3, Dc_6^0'=Dc_6^post3, __retres1_10^0'=__retres1_10^post3, __const_256^0'=__const_256^post3, lt_16^0'=lt_16^post3, ct_64^0'=ct_64^post3, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post3, lt_12^0'=lt_12^post3, cnt_34^0'=cnt_34^post3, ntStatus_8^0'=ntStatus_8^post3, lt_18^0'=lt_18^post3, __disjvr_1^0'=__disjvr_1^post3, (0 == 0 /\ -__disjvr_0^post3+__disjvr_0^0 == 0 /\ -__const_256^0+lt_13^10 <= 0 /\ -1+lt_16^110-cnt_29^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post3 == 0 /\ -__retres1_10^post3+__retres1_10^0 == 0 /\ Result_4^0-Result_4^post3 == 0 /\ -ntStatus_8^post3+ntStatus_8^0 == 0 /\ -cnt_34^0+lt_17^110 == 0 /\ 1+lt_16^110-lt_17^110 <= 0 /\ __const_256^0-lt_13^10 <= 0 /\ -Dc_6^post3+Dc_6^0 == 0 /\ lt_18^110-cnt_29^0 == 0 /\ -ct_115^0+lt_13^10 == 0 /\ 1-lt_14^110 <= 0 /\ -ct_64^post3+ct_64^0 == 0 /\ 1-lt_20^110+lt_19^110 <= 0 /\ -__const_256^post3+__const_256^0 == 0 /\ -ct_115^post3+ct_115^0 == 0 /\ -lt_12^post3+lt_12^0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post3 == 0 /\ -ct_115^0+lt_14^110 == 0 /\ -cnt_34^post3+cnt_34^0 == 0 /\ lt_20^110-cnt_34^0 == 0 /\ -__disjvr_1^post3+__disjvr_1^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post3 == 0 /\ -MaximumInterfaceType_9^post3+MaximumInterfaceType_9^0 == 0 /\ -cnt_29^0+lt_19^110 == 0 /\ cnt_29^0-cnt_29^post3 == 0), cost: 1
   5: l1 -> l4 : __cil_tmp2_11^0'=__cil_tmp2_11^post5, lt_14^0'=lt_14^post5, ct_15^0'=ct_15^post5, InterfaceType_5^0'=InterfaceType_5^post5, fdoExtension_7^0'=fdoExtension_7^post5, cnt_29^0'=cnt_29^post5, lt_20^0'=lt_20^post5, lt_17^0'=lt_17^post5, __disjvr_0^0'=__disjvr_0^post5, Result_4^0'=Result_4^post5, lt_13^0'=lt_13^post5, ct_115^0'=ct_115^post5, lt_19^0'=lt_19^post5, Dc_6^0'=Dc_6^post5, __retres1_10^0'=__retres1_10^post5, __const_256^0'=__const_256^post5, lt_16^0'=lt_16^post5, ct_64^0'=ct_64^post5, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post5, lt_12^0'=lt_12^post5, cnt_34^0'=cnt_34^post5, ntStatus_8^0'=ntStatus_8^post5, lt_18^0'=lt_18^post5, __disjvr_1^0'=__disjvr_1^post5, (0 == 0 /\ -__retres1_10^post5+__retres1_10^0 == 0 /\ -lt_12^post5+lt_12^0 == 0 /\ -ntStatus_8^post5+ntStatus_8^0 == 0 /\ lt_17^120-lt_16^120 <= 0 /\ ct_64^0-ct_64^post5 == 0 /\ -1-cnt_29^0+lt_16^120 == 0 /\ -cnt_29^0+lt_19^120 == 0 /\ InterfaceType_5^0-InterfaceType_5^post5 == 0 /\ -MaximumInterfaceType_9^post5+MaximumInterfaceType_9^0 == 0 /\ lt_17^120-cnt_34^0 == 0 /\ lt_20^120-cnt_34^0 == 0 /\ -Dc_6^post5+Dc_6^0 == 0 /\ -lt_13^post5+lt_13^0 == 0 /\ cnt_29^0-cnt_29^post5 == 0 /\ 1-lt_20^120+lt_19^120 <= 0 /\ Result_4^0-Result_4^post5 == 0 /\ -ct_64^0+lt_14^120 == 0 /\ -ct_115^post5+ct_115^0 == 0 /\ lt_14^120 <= 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post5 == 0 /\ -__disjvr_0^post5+__disjvr_0^0 == 0 /\ -cnt_34^post5+cnt_34^0 == 0 /\ -cnt_29^0+lt_18^120 == 0 /\ -__disjvr_1^post5+__disjvr_1^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post5 == 0 /\ __const_256^0-__const_256^post5 == 0), cost: 1
   7: l1 -> l5 : __cil_tmp2_11^0'=__cil_tmp2_11^post7, lt_14^0'=lt_14^post7, ct_15^0'=ct_15^post7, InterfaceType_5^0'=InterfaceType_5^post7, fdoExtension_7^0'=fdoExtension_7^post7, cnt_29^0'=cnt_29^post7, lt_20^0'=lt_20^post7, lt_17^0'=lt_17^post7, __disjvr_0^0'=__disjvr_0^post7, Result_4^0'=Result_4^post7, lt_13^0'=lt_13^post7, ct_115^0'=ct_115^post7, lt_19^0'=lt_19^post7, Dc_6^0'=Dc_6^post7, __retres1_10^0'=__retres1_10^post7, __const_256^0'=__const_256^post7, lt_16^0'=lt_16^post7, ct_64^0'=ct_64^post7, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post7, lt_12^0'=lt_12^post7, cnt_34^0'=cnt_34^post7, ntStatus_8^0'=ntStatus_8^post7, lt_18^0'=lt_18^post7, __disjvr_1^0'=__disjvr_1^post7, (0 == 0 /\ cnt_29^0-cnt_29^post7 == 0 /\ -__const_256^0+lt_13^110 <= 0 /\ -Result_4^post7+Result_4^0 == 0 /\ Dc_6^0-Dc_6^post7 == 0 /\ lt_17^130-lt_16^130 <= 0 /\ -1-cnt_29^0+lt_16^130 == 0 /\ -ntStatus_8^post7+ntStatus_8^0 == 0 /\ -lt_12^post7+lt_12^0 == 0 /\ __retres1_10^0-__retres1_10^post7 == 0 /\ lt_13^110-ct_64^0 == 0 /\ lt_17^130-cnt_34^0 == 0 /\ __const_256^0-lt_13^110 <= 0 /\ ct_115^0-ct_115^post7 == 0 /\ __const_256^0-__const_256^post7 == 0 /\ InterfaceType_5^0-InterfaceType_5^post7 == 0 /\ -MaximumInterfaceType_9^post7+MaximumInterfaceType_9^0 == 0 /\ -__disjvr_0^post7+__disjvr_0^0 == 0 /\ lt_18^130-cnt_29^0 == 0 /\ ct_64^0-ct_64^post7 == 0 /\ lt_14^130-ct_64^0 == 0 /\ -cnt_34^post7+cnt_34^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post7 == 0 /\ -__cil_tmp2_11^post7+__cil_tmp2_11^0 == 0 /\ -cnt_29^0+lt_19^130 == 0 /\ -__disjvr_1^post7+__disjvr_1^0 == 0 /\ 1-lt_14^130 <= 0 /\ 1-lt_20^130+lt_19^130 <= 0 /\ lt_20^130-cnt_34^0 == 0), cost: 1
   9: l1 -> l7 : __cil_tmp2_11^0'=__cil_tmp2_11^post9, lt_14^0'=lt_14^post9, ct_15^0'=ct_15^post9, InterfaceType_5^0'=InterfaceType_5^post9, fdoExtension_7^0'=fdoExtension_7^post9, cnt_29^0'=cnt_29^post9, lt_20^0'=lt_20^post9, lt_17^0'=lt_17^post9, __disjvr_0^0'=__disjvr_0^post9, Result_4^0'=Result_4^post9, lt_13^0'=lt_13^post9, ct_115^0'=ct_115^post9, lt_19^0'=lt_19^post9, Dc_6^0'=Dc_6^post9, __retres1_10^0'=__retres1_10^post9, __const_256^0'=__const_256^post9, lt_16^0'=lt_16^post9, ct_64^0'=ct_64^post9, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post9, lt_12^0'=lt_12^post9, cnt_34^0'=cnt_34^post9, ntStatus_8^0'=ntStatus_8^post9, lt_18^0'=lt_18^post9, __disjvr_1^0'=__disjvr_1^post9, (0 == 0 /\ Dc_6^0-Dc_6^post9 == 0 /\ lt_20^140-cnt_34^0 == 0 /\ -1-cnt_29^0+lt_16^140 == 0 /\ -ntStatus_8^post9+ntStatus_8^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post9 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post9 == 0 /\ ct_115^0-ct_115^post9 == 0 /\ cnt_29^0-cnt_29^post9 == 0 /\ 1-lt_17^140+lt_16^140 <= 0 /\ lt_14^140-ct_115^0 == 0 /\ -__const_256^post9+__const_256^0 == 0 /\ lt_17^140-cnt_34^0 == 0 /\ -__disjvr_0^post9+__disjvr_0^0 == 0 /\ -lt_12^post9+lt_12^0 == 0 /\ -MaximumInterfaceType_9^post9+MaximumInterfaceType_9^0 == 0 /\ -cnt_29^0+lt_19^140 == 0 /\ -ct_64^post9+ct_64^0 == 0 /\ -__disjvr_1^post9+__disjvr_1^0 == 0 /\ lt_13^post9-ct_115^0 == 0 /\ -__retres1_10^post9+__retres1_10^0 == 0 /\ -cnt_29^0+lt_18^140 == 0 /\ -cnt_34^post9+cnt_34^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post9 == 0 /\ Result_4^0-Result_4^post9 == 0 /\ 1-lt_14^140 <= 0 /\ 1+lt_19^140-lt_20^140 <= 0), cost: 1
  12: l1 -> l9 : __cil_tmp2_11^0'=__cil_tmp2_11^post12, lt_14^0'=lt_14^post12, ct_15^0'=ct_15^post12, InterfaceType_5^0'=InterfaceType_5^post12, fdoExtension_7^0'=fdoExtension_7^post12, cnt_29^0'=cnt_29^post12, lt_20^0'=lt_20^post12, lt_17^0'=lt_17^post12, __disjvr_0^0'=__disjvr_0^post12, Result_4^0'=Result_4^post12, lt_13^0'=lt_13^post12, ct_115^0'=ct_115^post12, lt_19^0'=lt_19^post12, Dc_6^0'=Dc_6^post12, __retres1_10^0'=__retres1_10^post12, __const_256^0'=__const_256^post12, lt_16^0'=lt_16^post12, ct_64^0'=ct_64^post12, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post12, lt_12^0'=lt_12^post12, cnt_34^0'=cnt_34^post12, ntStatus_8^0'=ntStatus_8^post12, lt_18^0'=lt_18^post12, __disjvr_1^0'=__disjvr_1^post12, (0 == 0 /\ lt_14^150-ct_64^0 == 0 /\ 1-lt_14^150 <= 0 /\ -1-cnt_29^0+lt_16^150 == 0 /\ lt_20^150-cnt_34^0 == 0 /\ ct_64^0-ct_64^post12 == 0 /\ InterfaceType_5^0-InterfaceType_5^post12 == 0 /\ -Result_4^post12+Result_4^0 == 0 /\ -__disjvr_1^post12+__disjvr_1^0 == 0 /\ ct_115^0-ct_115^post12 == 0 /\ -cnt_34^post12+cnt_34^0 == 0 /\ MaximumInterfaceType_9^0-MaximumInterfaceType_9^post12 == 0 /\ lt_13^post12-ct_64^0 == 0 /\ -ntStatus_8^post12+ntStatus_8^0 == 0 /\ __retres1_10^0-__retres1_10^post12 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post12 == 0 /\ -fdoExtension_7^post12+fdoExtension_7^0 == 0 /\ -cnt_29^0+lt_19^150 == 0 /\ -cnt_29^0+lt_18^150 == 0 /\ lt_17^150-lt_16^150 <= 0 /\ -lt_12^post12+lt_12^0 == 0 /\ -__const_256^post12+__const_256^0 == 0 /\ __disjvr_0^0-__disjvr_0^post12 == 0 /\ 1+lt_19^150-lt_20^150 <= 0 /\ cnt_29^0-cnt_29^post12 == 0 /\ lt_17^150-cnt_34^0 == 0 /\ Dc_6^0-Dc_6^post12 == 0), cost: 1
  15: l1 -> l11 : __cil_tmp2_11^0'=__cil_tmp2_11^post15, lt_14^0'=lt_14^post15, ct_15^0'=ct_15^post15, InterfaceType_5^0'=InterfaceType_5^post15, fdoExtension_7^0'=fdoExtension_7^post15, cnt_29^0'=cnt_29^post15, lt_20^0'=lt_20^post15, lt_17^0'=lt_17^post15, __disjvr_0^0'=__disjvr_0^post15, Result_4^0'=Result_4^post15, lt_13^0'=lt_13^post15, ct_115^0'=ct_115^post15, lt_19^0'=lt_19^post15, Dc_6^0'=Dc_6^post15, __retres1_10^0'=__retres1_10^post15, __const_256^0'=__const_256^post15, lt_16^0'=lt_16^post15, ct_64^0'=ct_64^post15, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post15, lt_12^0'=lt_12^post15, cnt_34^0'=cnt_34^post15, ntStatus_8^0'=ntStatus_8^post15, lt_18^0'=lt_18^post15, __disjvr_1^0'=__disjvr_1^post15, (0 == 0 /\ -lt_12^post15+lt_12^0 == 0 /\ cnt_29^0-cnt_29^post15 == 0 /\ __retres1_10^post15 == 0 /\ lt_17^0-lt_17^post15 == 0 /\ MaximumInterfaceType_9^0-MaximumInterfaceType_9^post15 == 0 /\ Result_4^post15-__cil_tmp2_11^post15 == 0 /\ -__disjvr_1^post15+__disjvr_1^0 == 0 /\ lt_13^0-lt_13^post15 == 0 /\ lt_20^160-lt_19^151 <= 0 /\ Dc_6^0-Dc_6^post15 == 0 /\ -lt_16^post15+lt_16^0 == 0 /\ -cnt_29^0+lt_19^151 == 0 /\ -cnt_34^post15+cnt_34^0 == 0 /\ ct_15^0-ct_15^post15 == 0 /\ lt_14^0-lt_14^post15 == 0 /\ -ntStatus_8^post15+ntStatus_8^0 == 0 /\ ct_115^0-ct_115^post15 == 0 /\ -ct_64^post15+ct_64^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post15 == 0 /\ -__retres1_10^post15+__cil_tmp2_11^post15 == 0 /\ lt_20^160-cnt_34^0 == 0 /\ -__const_256^post15+__const_256^0 == 0 /\ __disjvr_0^0-__disjvr_0^post15 == 0 /\ -fdoExtension_7^post15+fdoExtension_7^0 == 0 /\ lt_18^0-lt_18^post15 == 0), cost: 1
   2: l2 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post2, lt_14^0'=lt_14^post2, ct_15^0'=ct_15^post2, InterfaceType_5^0'=InterfaceType_5^post2, fdoExtension_7^0'=fdoExtension_7^post2, cnt_29^0'=cnt_29^post2, lt_20^0'=lt_20^post2, lt_17^0'=lt_17^post2, __disjvr_0^0'=__disjvr_0^post2, Result_4^0'=Result_4^post2, lt_13^0'=lt_13^post2, ct_115^0'=ct_115^post2, lt_19^0'=lt_19^post2, Dc_6^0'=Dc_6^post2, __retres1_10^0'=__retres1_10^post2, __const_256^0'=__const_256^post2, lt_16^0'=lt_16^post2, ct_64^0'=ct_64^post2, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post2, lt_12^0'=lt_12^post2, cnt_34^0'=cnt_34^post2, ntStatus_8^0'=ntStatus_8^post2, lt_18^0'=lt_18^post2, __disjvr_1^0'=__disjvr_1^post2, (ct_15^0-ct_15^post2 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post2 == 0 /\ -lt_12^post2+lt_12^0 == 0 /\ -lt_16^post2+lt_16^0 == 0 /\ lt_14^0-lt_14^post2 == 0 /\ MaximumInterfaceType_9^0-MaximumInterfaceType_9^post2 == 0 /\ -lt_13^post2+lt_13^0 == 0 /\ ct_115^0-ct_115^post2 == 0 /\ lt_17^0-lt_17^post2 == 0 /\ Result_4^0-Result_4^post2 == 0 /\ Dc_6^0-Dc_6^post2 == 0 /\ __disjvr_0^0-__disjvr_0^post2 == 0 /\ -cnt_34^post2+cnt_34^0 == 0 /\ -ntStatus_8^post2+ntStatus_8^0 == 0 /\ lt_20^0-lt_20^post2 == 0 /\ -cnt_29^post2+cnt_29^0 == 0 /\ -InterfaceType_5^post2+InterfaceType_5^0 == 0 /\ -__disjvr_1^post2+__disjvr_1^0 == 0 /\ -__const_256^post2+__const_256^0 == 0 /\ -__retres1_10^post2+__retres1_10^0 == 0 /\ lt_19^0-lt_19^post2 == 0 /\ fdoExtension_7^0-fdoExtension_7^post2 == 0 /\ -lt_18^post2+lt_18^0 == 0 /\ -ct_64^post2+ct_64^0 == 0), cost: 1
   4: l3 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post4, lt_14^0'=lt_14^post4, ct_15^0'=ct_15^post4, InterfaceType_5^0'=InterfaceType_5^post4, fdoExtension_7^0'=fdoExtension_7^post4, cnt_29^0'=cnt_29^post4, lt_20^0'=lt_20^post4, lt_17^0'=lt_17^post4, __disjvr_0^0'=__disjvr_0^post4, Result_4^0'=Result_4^post4, lt_13^0'=lt_13^post4, ct_115^0'=ct_115^post4, lt_19^0'=lt_19^post4, Dc_6^0'=Dc_6^post4, __retres1_10^0'=__retres1_10^post4, __const_256^0'=__const_256^post4, lt_16^0'=lt_16^post4, ct_64^0'=ct_64^post4, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post4, lt_12^0'=lt_12^post4, cnt_34^0'=cnt_34^post4, ntStatus_8^0'=ntStatus_8^post4, lt_18^0'=lt_18^post4, __disjvr_1^0'=__disjvr_1^post4, (-MaximumInterfaceType_9^post4+MaximumInterfaceType_9^0 == 0 /\ __disjvr_0^0-__disjvr_0^post4 == 0 /\ lt_12^0-lt_12^post4 == 0 /\ -lt_18^post4+lt_18^0 == 0 /\ -__disjvr_1^post4+__disjvr_1^0 == 0 /\ lt_17^0-lt_17^post4 == 0 /\ -fdoExtension_7^post4+fdoExtension_7^0 == 0 /\ lt_20^0-lt_20^post4 == 0 /\ -cnt_34^post4+cnt_34^0 == 0 /\ -lt_19^post4+lt_19^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post4 == 0 /\ -ntStatus_8^post4+ntStatus_8^0 == 0 /\ lt_14^0-lt_14^post4 == 0 /\ ct_15^0-ct_15^post4 == 0 /\ -__retres1_10^post4+__retres1_10^0 == 0 /\ -ct_64^post4+ct_64^0 == 0 /\ cnt_29^0-cnt_29^post4 == 0 /\ Dc_6^0-Dc_6^post4 == 0 /\ lt_16^0-lt_16^post4 == 0 /\ lt_13^0-lt_13^post4 == 0 /\ Result_4^0-Result_4^post4 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post4 == 0 /\ -__const_256^post4+__const_256^0 == 0 /\ -ct_115^post4+ct_115^0 == 0), cost: 1
   6: l4 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post6, lt_14^0'=lt_14^post6, ct_15^0'=ct_15^post6, InterfaceType_5^0'=InterfaceType_5^post6, fdoExtension_7^0'=fdoExtension_7^post6, cnt_29^0'=cnt_29^post6, lt_20^0'=lt_20^post6, lt_17^0'=lt_17^post6, __disjvr_0^0'=__disjvr_0^post6, Result_4^0'=Result_4^post6, lt_13^0'=lt_13^post6, ct_115^0'=ct_115^post6, lt_19^0'=lt_19^post6, Dc_6^0'=Dc_6^post6, __retres1_10^0'=__retres1_10^post6, __const_256^0'=__const_256^post6, lt_16^0'=lt_16^post6, ct_64^0'=ct_64^post6, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post6, lt_12^0'=lt_12^post6, cnt_34^0'=cnt_34^post6, ntStatus_8^0'=ntStatus_8^post6, lt_18^0'=lt_18^post6, __disjvr_1^0'=__disjvr_1^post6, (lt_13^0-lt_13^post6 == 0 /\ cnt_34^0-cnt_34^post6 == 0 /\ -Result_4^post6+Result_4^0 == 0 /\ -lt_19^post6+lt_19^0 == 0 /\ lt_20^0-lt_20^post6 == 0 /\ lt_12^0-lt_12^post6 == 0 /\ -ntStatus_8^post6+ntStatus_8^0 == 0 /\ -MaximumInterfaceType_9^post6+MaximumInterfaceType_9^0 == 0 /\ ct_15^0-ct_15^post6 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post6 == 0 /\ -ct_115^post6+ct_115^0 == 0 /\ lt_14^0-lt_14^post6 == 0 /\ InterfaceType_5^0-InterfaceType_5^post6 == 0 /\ -__const_256^post6+__const_256^0 == 0 /\ ct_64^0-ct_64^post6 == 0 /\ lt_17^0-lt_17^post6 == 0 /\ -fdoExtension_7^post6+fdoExtension_7^0 == 0 /\ -lt_18^post6+lt_18^0 == 0 /\ -__disjvr_1^post6+__disjvr_1^0 == 0 /\ -__retres1_10^post6+__retres1_10^0 == 0 /\ Dc_6^0-Dc_6^post6 == 0 /\ cnt_29^0-cnt_29^post6 == 0 /\ lt_16^0-lt_16^post6 == 0 /\ __disjvr_0^0-__disjvr_0^post6 == 0), cost: 1
   8: l5 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post8, lt_14^0'=lt_14^post8, ct_15^0'=ct_15^post8, InterfaceType_5^0'=InterfaceType_5^post8, fdoExtension_7^0'=fdoExtension_7^post8, cnt_29^0'=cnt_29^post8, lt_20^0'=lt_20^post8, lt_17^0'=lt_17^post8, __disjvr_0^0'=__disjvr_0^post8, Result_4^0'=Result_4^post8, lt_13^0'=lt_13^post8, ct_115^0'=ct_115^post8, lt_19^0'=lt_19^post8, Dc_6^0'=Dc_6^post8, __retres1_10^0'=__retres1_10^post8, __const_256^0'=__const_256^post8, lt_16^0'=lt_16^post8, ct_64^0'=ct_64^post8, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post8, lt_12^0'=lt_12^post8, cnt_34^0'=cnt_34^post8, ntStatus_8^0'=ntStatus_8^post8, lt_18^0'=lt_18^post8, __disjvr_1^0'=__disjvr_1^post8, (-__retres1_10^post8+__retres1_10^0 == 0 /\ -lt_16^post8+lt_16^0 == 0 /\ cnt_29^0-cnt_29^post8 == 0 /\ -ct_64^post8+ct_64^0 == 0 /\ lt_20^0-lt_20^post8 == 0 /\ -lt_12^post8+lt_12^0 == 0 /\ -Dc_6^post8+Dc_6^0 == 0 /\ -ntStatus_8^post8+ntStatus_8^0 == 0 /\ -lt_13^post8+lt_13^0 == 0 /\ -MaximumInterfaceType_9^post8+MaximumInterfaceType_9^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post8 == 0 /\ lt_14^0-lt_14^post8 == 0 /\ __const_256^0-__const_256^post8 == 0 /\ ct_115^0-ct_115^post8 == 0 /\ -cnt_34^post8+cnt_34^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post8 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post8 == 0 /\ Result_4^0-Result_4^post8 == 0 /\ lt_19^0-lt_19^post8 == 0 /\ __disjvr_0^0-__disjvr_0^post8 == 0 /\ -lt_17^post8+lt_17^0 == 0 /\ ct_15^0-ct_15^post8 == 0 /\ -__disjvr_1^post8+__disjvr_1^0 == 0 /\ lt_18^0-lt_18^post8 == 0), cost: 1
  10: l7 -> l8 : __cil_tmp2_11^0'=__cil_tmp2_11^post10, lt_14^0'=lt_14^post10, ct_15^0'=ct_15^post10, InterfaceType_5^0'=InterfaceType_5^post10, fdoExtension_7^0'=fdoExtension_7^post10, cnt_29^0'=cnt_29^post10, lt_20^0'=lt_20^post10, lt_17^0'=lt_17^post10, __disjvr_0^0'=__disjvr_0^post10, Result_4^0'=Result_4^post10, lt_13^0'=lt_13^post10, ct_115^0'=ct_115^post10, lt_19^0'=lt_19^post10, Dc_6^0'=Dc_6^post10, __retres1_10^0'=__retres1_10^post10, __const_256^0'=__const_256^post10, lt_16^0'=lt_16^post10, ct_64^0'=ct_64^post10, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post10, lt_12^0'=lt_12^post10, cnt_34^0'=cnt_34^post10, ntStatus_8^0'=ntStatus_8^post10, lt_18^0'=lt_18^post10, __disjvr_1^0'=__disjvr_1^post10, (lt_14^0-lt_14^post10 == 0 /\ -ct_64^post10+ct_64^0 == 0 /\ -__retres1_10^post10+__retres1_10^0 == 0 /\ -__const_256^post10+__const_256^0 == 0 /\ -lt_16^post10+lt_16^0 == 0 /\ -__disjvr_0^0+__disjvr_0^post10 == 0 /\ Dc_6^0-Dc_6^post10 == 0 /\ -cnt_34^post10+cnt_34^0 == 0 /\ -lt_19^post10+lt_19^0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post10 == 0 /\ Result_4^0-Result_4^post10 == 0 /\ -ntStatus_8^post10+ntStatus_8^0 == 0 /\ -lt_12^post10+lt_12^0 == 0 /\ ct_115^0-ct_115^post10 == 0 /\ __disjvr_0^0-__disjvr_0^post10 == 0 /\ ct_15^0-ct_15^post10 == 0 /\ lt_17^0-lt_17^post10 == 0 /\ cnt_29^0-cnt_29^post10 == 0 /\ -InterfaceType_5^post10+InterfaceType_5^0 == 0 /\ -lt_18^post10+lt_18^0 == 0 /\ lt_20^0-lt_20^post10 == 0 /\ -MaximumInterfaceType_9^post10+MaximumInterfaceType_9^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post10 == 0 /\ lt_13^0-lt_13^post10 == 0 /\ -__disjvr_1^post10+__disjvr_1^0 == 0), cost: 1
  11: l8 -> l6 : __cil_tmp2_11^0'=__cil_tmp2_11^post11, lt_14^0'=lt_14^post11, ct_15^0'=ct_15^post11, InterfaceType_5^0'=InterfaceType_5^post11, fdoExtension_7^0'=fdoExtension_7^post11, cnt_29^0'=cnt_29^post11, lt_20^0'=lt_20^post11, lt_17^0'=lt_17^post11, __disjvr_0^0'=__disjvr_0^post11, Result_4^0'=Result_4^post11, lt_13^0'=lt_13^post11, ct_115^0'=ct_115^post11, lt_19^0'=lt_19^post11, Dc_6^0'=Dc_6^post11, __retres1_10^0'=__retres1_10^post11, __const_256^0'=__const_256^post11, lt_16^0'=lt_16^post11, ct_64^0'=ct_64^post11, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post11, lt_12^0'=lt_12^post11, cnt_34^0'=cnt_34^post11, ntStatus_8^0'=ntStatus_8^post11, lt_18^0'=lt_18^post11, __disjvr_1^0'=__disjvr_1^post11, (0 == 0 /\ -InterfaceType_5^post11+InterfaceType_5^0 == 0 /\ Dc_6^0-Dc_6^post11 == 0 /\ ct_115^0-ct_115^post11 == 0 /\ -__const_256^post11+__const_256^0 == 0 /\ -__disjvr_1^post11+__disjvr_1^0 == 0 /\ ct_15^0-ct_15^post11 == 0 /\ -lt_12^10+__retres1_10^post11 == 0 /\ lt_17^0-lt_17^post11 == 0 /\ -ct_64^post11+ct_64^0 == 0 /\ lt_12^10-ct_115^0 == 0 /\ lt_20^0-lt_20^post11 == 0 /\ Result_4^post11-__cil_tmp2_11^post11 == 0 /\ -__retres1_10^post11+__cil_tmp2_11^post11 == 0 /\ __disjvr_0^0-__disjvr_0^post11 == 0 /\ -lt_16^post11+lt_16^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post11 == 0 /\ cnt_29^0-cnt_29^post11 == 0 /\ -lt_18^post11+lt_18^0 == 0 /\ lt_14^0-lt_14^post11 == 0 /\ -lt_19^post11+lt_19^0 == 0 /\ -cnt_34^post11+cnt_34^0 == 0 /\ -ntStatus_8^post11+ntStatus_8^0 == 0 /\ -MaximumInterfaceType_9^post11+MaximumInterfaceType_9^0 == 0), cost: 1
  13: l9 -> l10 : __cil_tmp2_11^0'=__cil_tmp2_11^post13, lt_14^0'=lt_14^post13, ct_15^0'=ct_15^post13, InterfaceType_5^0'=InterfaceType_5^post13, fdoExtension_7^0'=fdoExtension_7^post13, cnt_29^0'=cnt_29^post13, lt_20^0'=lt_20^post13, lt_17^0'=lt_17^post13, __disjvr_0^0'=__disjvr_0^post13, Result_4^0'=Result_4^post13, lt_13^0'=lt_13^post13, ct_115^0'=ct_115^post13, lt_19^0'=lt_19^post13, Dc_6^0'=Dc_6^post13, __retres1_10^0'=__retres1_10^post13, __const_256^0'=__const_256^post13, lt_16^0'=lt_16^post13, ct_64^0'=ct_64^post13, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post13, lt_12^0'=lt_12^post13, cnt_34^0'=cnt_34^post13, ntStatus_8^0'=ntStatus_8^post13, lt_18^0'=lt_18^post13, __disjvr_1^0'=__disjvr_1^post13, (-cnt_29^post13+cnt_29^0 == 0 /\ -ntStatus_8^post13+ntStatus_8^0 == 0 /\ lt_19^0-lt_19^post13 == 0 /\ MaximumInterfaceType_9^0-MaximumInterfaceType_9^post13 == 0 /\ lt_20^0-lt_20^post13 == 0 /\ -lt_18^post13+lt_18^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post13 == 0 /\ -ct_64^post13+ct_64^0 == 0 /\ __const_256^0-__const_256^post13 == 0 /\ -lt_13^post13+lt_13^0 == 0 /\ -Dc_6^post13+Dc_6^0 == 0 /\ Result_4^0-Result_4^post13 == 0 /\ -lt_12^post13+lt_12^0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post13 == 0 /\ lt_14^0-lt_14^post13 == 0 /\ InterfaceType_5^0-InterfaceType_5^post13 == 0 /\ -lt_17^post13+lt_17^0 == 0 /\ ct_115^0-ct_115^post13 == 0 /\ -__disjvr_1^post13+__disjvr_1^0 == 0 /\ ct_15^0-ct_15^post13 == 0 /\ -lt_16^post13+lt_16^0 == 0 /\ -__retres1_10^post13+__retres1_10^0 == 0 /\ -cnt_34^post13+cnt_34^0 == 0 /\ __disjvr_0^0-__disjvr_0^post13 == 0 /\ __disjvr_1^post13-__disjvr_1^0 == 0), cost: 1
  14: l10 -> l6 : __cil_tmp2_11^0'=__cil_tmp2_11^post14, lt_14^0'=lt_14^post14, ct_15^0'=ct_15^post14, InterfaceType_5^0'=InterfaceType_5^post14, fdoExtension_7^0'=fdoExtension_7^post14, cnt_29^0'=cnt_29^post14, lt_20^0'=lt_20^post14, lt_17^0'=lt_17^post14, __disjvr_0^0'=__disjvr_0^post14, Result_4^0'=Result_4^post14, lt_13^0'=lt_13^post14, ct_115^0'=ct_115^post14, lt_19^0'=lt_19^post14, Dc_6^0'=Dc_6^post14, __retres1_10^0'=__retres1_10^post14, __const_256^0'=__const_256^post14, lt_16^0'=lt_16^post14, ct_64^0'=ct_64^post14, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post14, lt_12^0'=lt_12^post14, cnt_34^0'=cnt_34^post14, ntStatus_8^0'=ntStatus_8^post14, lt_18^0'=lt_18^post14, __disjvr_1^0'=__disjvr_1^post14, (0 == 0 /\ __disjvr_0^0-__disjvr_0^post14 == 0 /\ -__disjvr_1^post14+__disjvr_1^0 == 0 /\ ct_15^0-ct_15^post14 == 0 /\ -lt_18^post14+lt_18^0 == 0 /\ cnt_34^0-cnt_34^post14 == 0 /\ lt_17^0-lt_17^post14 == 0 /\ -MaximumInterfaceType_9^post14+MaximumInterfaceType_9^0 == 0 /\ -fdoExtension_7^post14+fdoExtension_7^0 == 0 /\ lt_16^0-lt_16^post14 == 0 /\ -__const_256^post14+__const_256^0 == 0 /\ Dc_6^0-Dc_6^post14 == 0 /\ InterfaceType_5^0-InterfaceType_5^post14 == 0 /\ lt_20^0-lt_20^post14 == 0 /\ cnt_29^0-cnt_29^post14 == 0 /\ lt_14^0-lt_14^post14 == 0 /\ ct_64^0-ct_64^post14 == 0 /\ lt_12^11-ct_64^0 == 0 /\ -ntStatus_8^post14+ntStatus_8^0 == 0 /\ -__cil_tmp2_11^post14+Result_4^post14 == 0 /\ -lt_19^post14+lt_19^0 == 0 /\ -__retres1_10^post14+__cil_tmp2_11^post14 == 0 /\ __retres1_10^post14-lt_12^11 == 0 /\ -ct_115^post14+ct_115^0 == 0), cost: 1
  16: l12 -> l0 : __cil_tmp2_11^0'=__cil_tmp2_11^post16, lt_14^0'=lt_14^post16, ct_15^0'=ct_15^post16, InterfaceType_5^0'=InterfaceType_5^post16, fdoExtension_7^0'=fdoExtension_7^post16, cnt_29^0'=cnt_29^post16, lt_20^0'=lt_20^post16, lt_17^0'=lt_17^post16, __disjvr_0^0'=__disjvr_0^post16, Result_4^0'=Result_4^post16, lt_13^0'=lt_13^post16, ct_115^0'=ct_115^post16, lt_19^0'=lt_19^post16, Dc_6^0'=Dc_6^post16, __retres1_10^0'=__retres1_10^post16, __const_256^0'=__const_256^post16, lt_16^0'=lt_16^post16, ct_64^0'=ct_64^post16, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post16, lt_12^0'=lt_12^post16, cnt_34^0'=cnt_34^post16, ntStatus_8^0'=ntStatus_8^post16, lt_18^0'=lt_18^post16, __disjvr_1^0'=__disjvr_1^post16, (lt_13^0-lt_13^post16 == 0 /\ cnt_34^0-cnt_34^post16 == 0 /\ -Result_4^post16+Result_4^0 == 0 /\ lt_20^0-lt_20^post16 == 0 /\ lt_12^0-lt_12^post16 == 0 /\ -ntStatus_8^post16+ntStatus_8^0 == 0 /\ -MaximumInterfaceType_9^post16+MaximumInterfaceType_9^0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post16 == 0 /\ lt_14^0-lt_14^post16 == 0 /\ ct_15^0-ct_15^post16 == 0 /\ -ct_115^post16+ct_115^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post16 == 0 /\ -lt_19^post16+lt_19^0 == 0 /\ ct_64^0-ct_64^post16 == 0 /\ -__const_256^post16+__const_256^0 == 0 /\ -lt_18^post16+lt_18^0 == 0 /\ -fdoExtension_7^post16+fdoExtension_7^0 == 0 /\ -__disjvr_1^post16+__disjvr_1^0 == 0 /\ lt_17^0-lt_17^post16 == 0 /\ cnt_29^0-cnt_29^post16 == 0 /\ Dc_6^0-Dc_6^post16 == 0 /\ -__retres1_10^post16+__retres1_10^0 == 0 /\ lt_16^0-lt_16^post16 == 0 /\ __disjvr_0^0-__disjvr_0^post16 == 0), cost: 1


Removed unreachable rules and leafs
Start location: l12
   0: l0 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post0, lt_14^0'=lt_14^post0, ct_15^0'=ct_15^post0, InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, cnt_29^0'=cnt_29^post0, lt_20^0'=lt_20^post0, lt_17^0'=lt_17^post0, __disjvr_0^0'=__disjvr_0^post0, Result_4^0'=Result_4^post0, lt_13^0'=lt_13^post0, ct_115^0'=ct_115^post0, lt_19^0'=lt_19^post0, Dc_6^0'=Dc_6^post0, __retres1_10^0'=__retres1_10^post0, __const_256^0'=__const_256^post0, lt_16^0'=lt_16^post0, ct_64^0'=ct_64^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, lt_12^0'=lt_12^post0, cnt_34^0'=cnt_34^post0, ntStatus_8^0'=ntStatus_8^post0, lt_18^0'=lt_18^post0, __disjvr_1^0'=__disjvr_1^post0, (0 == 0 /\ -lt_18^post0+lt_18^0 == 0 /\ __disjvr_0^0-__disjvr_0^post0 == 0 /\ lt_12^0-lt_12^post0 == 0 /\ -__disjvr_1^post0+__disjvr_1^0 == 0 /\ lt_13^0-lt_13^post0 == 0 /\ lt_17^0-lt_17^post0 == 0 /\ -cnt_34^post0+cnt_34^0 == 0 /\ lt_20^0-lt_20^post0 == 0 /\ -lt_19^post0+lt_19^0 == 0 /\ -Result_4^post0+Result_4^0 == 0 /\ -ct_64^post0+ct_64^0 == 0 /\ -__retres1_10^post0+__retres1_10^0 == 0 /\ lt_14^0-lt_14^post0 == 0 /\ ct_15^0-ct_15^post0 == 0 /\ lt_16^0-lt_16^post0 == 0 /\ cnt_29^0-cnt_29^post0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post0 == 0 /\ -__const_256^post0+__const_256^0 == 0 /\ -ct_115^post0+ct_115^0 == 0), cost: 1
   1: l1 -> l2 : __cil_tmp2_11^0'=__cil_tmp2_11^post1, lt_14^0'=lt_14^post1, ct_15^0'=ct_15^post1, InterfaceType_5^0'=InterfaceType_5^post1, fdoExtension_7^0'=fdoExtension_7^post1, cnt_29^0'=cnt_29^post1, lt_20^0'=lt_20^post1, lt_17^0'=lt_17^post1, __disjvr_0^0'=__disjvr_0^post1, Result_4^0'=Result_4^post1, lt_13^0'=lt_13^post1, ct_115^0'=ct_115^post1, lt_19^0'=lt_19^post1, Dc_6^0'=Dc_6^post1, __retres1_10^0'=__retres1_10^post1, __const_256^0'=__const_256^post1, lt_16^0'=lt_16^post1, ct_64^0'=ct_64^post1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post1, lt_12^0'=lt_12^post1, cnt_34^0'=cnt_34^post1, ntStatus_8^0'=ntStatus_8^post1, lt_18^0'=lt_18^post1, __disjvr_1^0'=__disjvr_1^post1, (0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post1 == 0 /\ lt_13^0-lt_13^post1 == 0 /\ -1+lt_16^10-cnt_29^0 == 0 /\ -ntStatus_8^post1+ntStatus_8^0 == 0 /\ 1+lt_16^10-lt_17^10 <= 0 /\ lt_17^10-cnt_34^0 == 0 /\ cnt_34^0-cnt_34^post1 == 0 /\ -lt_12^post1+lt_12^0 == 0 /\ -__retres1_10^post1+__retres1_10^0 == 0 /\ 1-lt_20^10+lt_19^10 <= 0 /\ lt_20^10-cnt_34^0 == 0 /\ -__const_256^post1+__const_256^0 == 0 /\ cnt_29^0-cnt_29^post1 == 0 /\ Dc_6^0-Dc_6^post1 == 0 /\ -cnt_29^0+lt_18^10 == 0 /\ -cnt_29^0+lt_19^10 == 0 /\ Result_4^0-Result_4^post1 == 0 /\ InterfaceType_5^0-InterfaceType_5^post1 == 0 /\ -ct_115^post1+ct_115^0 == 0 /\ ct_64^0-ct_64^post1 == 0 /\ -fdoExtension_7^post1+fdoExtension_7^0 == 0 /\ -ct_115^0+lt_14^10 == 0 /\ -__disjvr_1^post1+__disjvr_1^0 == 0 /\ -MaximumInterfaceType_9^post1+MaximumInterfaceType_9^0 == 0 /\ __disjvr_0^0-__disjvr_0^post1 == 0 /\ lt_14^10 <= 0), cost: 1
   3: l1 -> l3 : __cil_tmp2_11^0'=__cil_tmp2_11^post3, lt_14^0'=lt_14^post3, ct_15^0'=ct_15^post3, InterfaceType_5^0'=InterfaceType_5^post3, fdoExtension_7^0'=fdoExtension_7^post3, cnt_29^0'=cnt_29^post3, lt_20^0'=lt_20^post3, lt_17^0'=lt_17^post3, __disjvr_0^0'=__disjvr_0^post3, Result_4^0'=Result_4^post3, lt_13^0'=lt_13^post3, ct_115^0'=ct_115^post3, lt_19^0'=lt_19^post3, Dc_6^0'=Dc_6^post3, __retres1_10^0'=__retres1_10^post3, __const_256^0'=__const_256^post3, lt_16^0'=lt_16^post3, ct_64^0'=ct_64^post3, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post3, lt_12^0'=lt_12^post3, cnt_34^0'=cnt_34^post3, ntStatus_8^0'=ntStatus_8^post3, lt_18^0'=lt_18^post3, __disjvr_1^0'=__disjvr_1^post3, (0 == 0 /\ -__disjvr_0^post3+__disjvr_0^0 == 0 /\ -__const_256^0+lt_13^10 <= 0 /\ -1+lt_16^110-cnt_29^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post3 == 0 /\ -__retres1_10^post3+__retres1_10^0 == 0 /\ Result_4^0-Result_4^post3 == 0 /\ -ntStatus_8^post3+ntStatus_8^0 == 0 /\ -cnt_34^0+lt_17^110 == 0 /\ 1+lt_16^110-lt_17^110 <= 0 /\ __const_256^0-lt_13^10 <= 0 /\ -Dc_6^post3+Dc_6^0 == 0 /\ lt_18^110-cnt_29^0 == 0 /\ -ct_115^0+lt_13^10 == 0 /\ 1-lt_14^110 <= 0 /\ -ct_64^post3+ct_64^0 == 0 /\ 1-lt_20^110+lt_19^110 <= 0 /\ -__const_256^post3+__const_256^0 == 0 /\ -ct_115^post3+ct_115^0 == 0 /\ -lt_12^post3+lt_12^0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post3 == 0 /\ -ct_115^0+lt_14^110 == 0 /\ -cnt_34^post3+cnt_34^0 == 0 /\ lt_20^110-cnt_34^0 == 0 /\ -__disjvr_1^post3+__disjvr_1^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post3 == 0 /\ -MaximumInterfaceType_9^post3+MaximumInterfaceType_9^0 == 0 /\ -cnt_29^0+lt_19^110 == 0 /\ cnt_29^0-cnt_29^post3 == 0), cost: 1
   5: l1 -> l4 : __cil_tmp2_11^0'=__cil_tmp2_11^post5, lt_14^0'=lt_14^post5, ct_15^0'=ct_15^post5, InterfaceType_5^0'=InterfaceType_5^post5, fdoExtension_7^0'=fdoExtension_7^post5, cnt_29^0'=cnt_29^post5, lt_20^0'=lt_20^post5, lt_17^0'=lt_17^post5, __disjvr_0^0'=__disjvr_0^post5, Result_4^0'=Result_4^post5, lt_13^0'=lt_13^post5, ct_115^0'=ct_115^post5, lt_19^0'=lt_19^post5, Dc_6^0'=Dc_6^post5, __retres1_10^0'=__retres1_10^post5, __const_256^0'=__const_256^post5, lt_16^0'=lt_16^post5, ct_64^0'=ct_64^post5, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post5, lt_12^0'=lt_12^post5, cnt_34^0'=cnt_34^post5, ntStatus_8^0'=ntStatus_8^post5, lt_18^0'=lt_18^post5, __disjvr_1^0'=__disjvr_1^post5, (0 == 0 /\ -__retres1_10^post5+__retres1_10^0 == 0 /\ -lt_12^post5+lt_12^0 == 0 /\ -ntStatus_8^post5+ntStatus_8^0 == 0 /\ lt_17^120-lt_16^120 <= 0 /\ ct_64^0-ct_64^post5 == 0 /\ -1-cnt_29^0+lt_16^120 == 0 /\ -cnt_29^0+lt_19^120 == 0 /\ InterfaceType_5^0-InterfaceType_5^post5 == 0 /\ -MaximumInterfaceType_9^post5+MaximumInterfaceType_9^0 == 0 /\ lt_17^120-cnt_34^0 == 0 /\ lt_20^120-cnt_34^0 == 0 /\ -Dc_6^post5+Dc_6^0 == 0 /\ -lt_13^post5+lt_13^0 == 0 /\ cnt_29^0-cnt_29^post5 == 0 /\ 1-lt_20^120+lt_19^120 <= 0 /\ Result_4^0-Result_4^post5 == 0 /\ -ct_64^0+lt_14^120 == 0 /\ -ct_115^post5+ct_115^0 == 0 /\ lt_14^120 <= 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post5 == 0 /\ -__disjvr_0^post5+__disjvr_0^0 == 0 /\ -cnt_34^post5+cnt_34^0 == 0 /\ -cnt_29^0+lt_18^120 == 0 /\ -__disjvr_1^post5+__disjvr_1^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post5 == 0 /\ __const_256^0-__const_256^post5 == 0), cost: 1
   7: l1 -> l5 : __cil_tmp2_11^0'=__cil_tmp2_11^post7, lt_14^0'=lt_14^post7, ct_15^0'=ct_15^post7, InterfaceType_5^0'=InterfaceType_5^post7, fdoExtension_7^0'=fdoExtension_7^post7, cnt_29^0'=cnt_29^post7, lt_20^0'=lt_20^post7, lt_17^0'=lt_17^post7, __disjvr_0^0'=__disjvr_0^post7, Result_4^0'=Result_4^post7, lt_13^0'=lt_13^post7, ct_115^0'=ct_115^post7, lt_19^0'=lt_19^post7, Dc_6^0'=Dc_6^post7, __retres1_10^0'=__retres1_10^post7, __const_256^0'=__const_256^post7, lt_16^0'=lt_16^post7, ct_64^0'=ct_64^post7, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post7, lt_12^0'=lt_12^post7, cnt_34^0'=cnt_34^post7, ntStatus_8^0'=ntStatus_8^post7, lt_18^0'=lt_18^post7, __disjvr_1^0'=__disjvr_1^post7, (0 == 0 /\ cnt_29^0-cnt_29^post7 == 0 /\ -__const_256^0+lt_13^110 <= 0 /\ -Result_4^post7+Result_4^0 == 0 /\ Dc_6^0-Dc_6^post7 == 0 /\ lt_17^130-lt_16^130 <= 0 /\ -1-cnt_29^0+lt_16^130 == 0 /\ -ntStatus_8^post7+ntStatus_8^0 == 0 /\ -lt_12^post7+lt_12^0 == 0 /\ __retres1_10^0-__retres1_10^post7 == 0 /\ lt_13^110-ct_64^0 == 0 /\ lt_17^130-cnt_34^0 == 0 /\ __const_256^0-lt_13^110 <= 0 /\ ct_115^0-ct_115^post7 == 0 /\ __const_256^0-__const_256^post7 == 0 /\ InterfaceType_5^0-InterfaceType_5^post7 == 0 /\ -MaximumInterfaceType_9^post7+MaximumInterfaceType_9^0 == 0 /\ -__disjvr_0^post7+__disjvr_0^0 == 0 /\ lt_18^130-cnt_29^0 == 0 /\ ct_64^0-ct_64^post7 == 0 /\ lt_14^130-ct_64^0 == 0 /\ -cnt_34^post7+cnt_34^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post7 == 0 /\ -__cil_tmp2_11^post7+__cil_tmp2_11^0 == 0 /\ -cnt_29^0+lt_19^130 == 0 /\ -__disjvr_1^post7+__disjvr_1^0 == 0 /\ 1-lt_14^130 <= 0 /\ 1-lt_20^130+lt_19^130 <= 0 /\ lt_20^130-cnt_34^0 == 0), cost: 1
   2: l2 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post2, lt_14^0'=lt_14^post2, ct_15^0'=ct_15^post2, InterfaceType_5^0'=InterfaceType_5^post2, fdoExtension_7^0'=fdoExtension_7^post2, cnt_29^0'=cnt_29^post2, lt_20^0'=lt_20^post2, lt_17^0'=lt_17^post2, __disjvr_0^0'=__disjvr_0^post2, Result_4^0'=Result_4^post2, lt_13^0'=lt_13^post2, ct_115^0'=ct_115^post2, lt_19^0'=lt_19^post2, Dc_6^0'=Dc_6^post2, __retres1_10^0'=__retres1_10^post2, __const_256^0'=__const_256^post2, lt_16^0'=lt_16^post2, ct_64^0'=ct_64^post2, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post2, lt_12^0'=lt_12^post2, cnt_34^0'=cnt_34^post2, ntStatus_8^0'=ntStatus_8^post2, lt_18^0'=lt_18^post2, __disjvr_1^0'=__disjvr_1^post2, (ct_15^0-ct_15^post2 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post2 == 0 /\ -lt_12^post2+lt_12^0 == 0 /\ -lt_16^post2+lt_16^0 == 0 /\ lt_14^0-lt_14^post2 == 0 /\ MaximumInterfaceType_9^0-MaximumInterfaceType_9^post2 == 0 /\ -lt_13^post2+lt_13^0 == 0 /\ ct_115^0-ct_115^post2 == 0 /\ lt_17^0-lt_17^post2 == 0 /\ Result_4^0-Result_4^post2 == 0 /\ Dc_6^0-Dc_6^post2 == 0 /\ __disjvr_0^0-__disjvr_0^post2 == 0 /\ -cnt_34^post2+cnt_34^0 == 0 /\ -ntStatus_8^post2+ntStatus_8^0 == 0 /\ lt_20^0-lt_20^post2 == 0 /\ -cnt_29^post2+cnt_29^0 == 0 /\ -InterfaceType_5^post2+InterfaceType_5^0 == 0 /\ -__disjvr_1^post2+__disjvr_1^0 == 0 /\ -__const_256^post2+__const_256^0 == 0 /\ -__retres1_10^post2+__retres1_10^0 == 0 /\ lt_19^0-lt_19^post2 == 0 /\ fdoExtension_7^0-fdoExtension_7^post2 == 0 /\ -lt_18^post2+lt_18^0 == 0 /\ -ct_64^post2+ct_64^0 == 0), cost: 1
   4: l3 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post4, lt_14^0'=lt_14^post4, ct_15^0'=ct_15^post4, InterfaceType_5^0'=InterfaceType_5^post4, fdoExtension_7^0'=fdoExtension_7^post4, cnt_29^0'=cnt_29^post4, lt_20^0'=lt_20^post4, lt_17^0'=lt_17^post4, __disjvr_0^0'=__disjvr_0^post4, Result_4^0'=Result_4^post4, lt_13^0'=lt_13^post4, ct_115^0'=ct_115^post4, lt_19^0'=lt_19^post4, Dc_6^0'=Dc_6^post4, __retres1_10^0'=__retres1_10^post4, __const_256^0'=__const_256^post4, lt_16^0'=lt_16^post4, ct_64^0'=ct_64^post4, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post4, lt_12^0'=lt_12^post4, cnt_34^0'=cnt_34^post4, ntStatus_8^0'=ntStatus_8^post4, lt_18^0'=lt_18^post4, __disjvr_1^0'=__disjvr_1^post4, (-MaximumInterfaceType_9^post4+MaximumInterfaceType_9^0 == 0 /\ __disjvr_0^0-__disjvr_0^post4 == 0 /\ lt_12^0-lt_12^post4 == 0 /\ -lt_18^post4+lt_18^0 == 0 /\ -__disjvr_1^post4+__disjvr_1^0 == 0 /\ lt_17^0-lt_17^post4 == 0 /\ -fdoExtension_7^post4+fdoExtension_7^0 == 0 /\ lt_20^0-lt_20^post4 == 0 /\ -cnt_34^post4+cnt_34^0 == 0 /\ -lt_19^post4+lt_19^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post4 == 0 /\ -ntStatus_8^post4+ntStatus_8^0 == 0 /\ lt_14^0-lt_14^post4 == 0 /\ ct_15^0-ct_15^post4 == 0 /\ -__retres1_10^post4+__retres1_10^0 == 0 /\ -ct_64^post4+ct_64^0 == 0 /\ cnt_29^0-cnt_29^post4 == 0 /\ Dc_6^0-Dc_6^post4 == 0 /\ lt_16^0-lt_16^post4 == 0 /\ lt_13^0-lt_13^post4 == 0 /\ Result_4^0-Result_4^post4 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post4 == 0 /\ -__const_256^post4+__const_256^0 == 0 /\ -ct_115^post4+ct_115^0 == 0), cost: 1
   6: l4 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post6, lt_14^0'=lt_14^post6, ct_15^0'=ct_15^post6, InterfaceType_5^0'=InterfaceType_5^post6, fdoExtension_7^0'=fdoExtension_7^post6, cnt_29^0'=cnt_29^post6, lt_20^0'=lt_20^post6, lt_17^0'=lt_17^post6, __disjvr_0^0'=__disjvr_0^post6, Result_4^0'=Result_4^post6, lt_13^0'=lt_13^post6, ct_115^0'=ct_115^post6, lt_19^0'=lt_19^post6, Dc_6^0'=Dc_6^post6, __retres1_10^0'=__retres1_10^post6, __const_256^0'=__const_256^post6, lt_16^0'=lt_16^post6, ct_64^0'=ct_64^post6, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post6, lt_12^0'=lt_12^post6, cnt_34^0'=cnt_34^post6, ntStatus_8^0'=ntStatus_8^post6, lt_18^0'=lt_18^post6, __disjvr_1^0'=__disjvr_1^post6, (lt_13^0-lt_13^post6 == 0 /\ cnt_34^0-cnt_34^post6 == 0 /\ -Result_4^post6+Result_4^0 == 0 /\ -lt_19^post6+lt_19^0 == 0 /\ lt_20^0-lt_20^post6 == 0 /\ lt_12^0-lt_12^post6 == 0 /\ -ntStatus_8^post6+ntStatus_8^0 == 0 /\ -MaximumInterfaceType_9^post6+MaximumInterfaceType_9^0 == 0 /\ ct_15^0-ct_15^post6 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post6 == 0 /\ -ct_115^post6+ct_115^0 == 0 /\ lt_14^0-lt_14^post6 == 0 /\ InterfaceType_5^0-InterfaceType_5^post6 == 0 /\ -__const_256^post6+__const_256^0 == 0 /\ ct_64^0-ct_64^post6 == 0 /\ lt_17^0-lt_17^post6 == 0 /\ -fdoExtension_7^post6+fdoExtension_7^0 == 0 /\ -lt_18^post6+lt_18^0 == 0 /\ -__disjvr_1^post6+__disjvr_1^0 == 0 /\ -__retres1_10^post6+__retres1_10^0 == 0 /\ Dc_6^0-Dc_6^post6 == 0 /\ cnt_29^0-cnt_29^post6 == 0 /\ lt_16^0-lt_16^post6 == 0 /\ __disjvr_0^0-__disjvr_0^post6 == 0), cost: 1
   8: l5 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post8, lt_14^0'=lt_14^post8, ct_15^0'=ct_15^post8, InterfaceType_5^0'=InterfaceType_5^post8, fdoExtension_7^0'=fdoExtension_7^post8, cnt_29^0'=cnt_29^post8, lt_20^0'=lt_20^post8, lt_17^0'=lt_17^post8, __disjvr_0^0'=__disjvr_0^post8, Result_4^0'=Result_4^post8, lt_13^0'=lt_13^post8, ct_115^0'=ct_115^post8, lt_19^0'=lt_19^post8, Dc_6^0'=Dc_6^post8, __retres1_10^0'=__retres1_10^post8, __const_256^0'=__const_256^post8, lt_16^0'=lt_16^post8, ct_64^0'=ct_64^post8, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post8, lt_12^0'=lt_12^post8, cnt_34^0'=cnt_34^post8, ntStatus_8^0'=ntStatus_8^post8, lt_18^0'=lt_18^post8, __disjvr_1^0'=__disjvr_1^post8, (-__retres1_10^post8+__retres1_10^0 == 0 /\ -lt_16^post8+lt_16^0 == 0 /\ cnt_29^0-cnt_29^post8 == 0 /\ -ct_64^post8+ct_64^0 == 0 /\ lt_20^0-lt_20^post8 == 0 /\ -lt_12^post8+lt_12^0 == 0 /\ -Dc_6^post8+Dc_6^0 == 0 /\ -ntStatus_8^post8+ntStatus_8^0 == 0 /\ -lt_13^post8+lt_13^0 == 0 /\ -MaximumInterfaceType_9^post8+MaximumInterfaceType_9^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post8 == 0 /\ lt_14^0-lt_14^post8 == 0 /\ __const_256^0-__const_256^post8 == 0 /\ ct_115^0-ct_115^post8 == 0 /\ -cnt_34^post8+cnt_34^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post8 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post8 == 0 /\ Result_4^0-Result_4^post8 == 0 /\ lt_19^0-lt_19^post8 == 0 /\ __disjvr_0^0-__disjvr_0^post8 == 0 /\ -lt_17^post8+lt_17^0 == 0 /\ ct_15^0-ct_15^post8 == 0 /\ -__disjvr_1^post8+__disjvr_1^0 == 0 /\ lt_18^0-lt_18^post8 == 0), cost: 1
  16: l12 -> l0 : __cil_tmp2_11^0'=__cil_tmp2_11^post16, lt_14^0'=lt_14^post16, ct_15^0'=ct_15^post16, InterfaceType_5^0'=InterfaceType_5^post16, fdoExtension_7^0'=fdoExtension_7^post16, cnt_29^0'=cnt_29^post16, lt_20^0'=lt_20^post16, lt_17^0'=lt_17^post16, __disjvr_0^0'=__disjvr_0^post16, Result_4^0'=Result_4^post16, lt_13^0'=lt_13^post16, ct_115^0'=ct_115^post16, lt_19^0'=lt_19^post16, Dc_6^0'=Dc_6^post16, __retres1_10^0'=__retres1_10^post16, __const_256^0'=__const_256^post16, lt_16^0'=lt_16^post16, ct_64^0'=ct_64^post16, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post16, lt_12^0'=lt_12^post16, cnt_34^0'=cnt_34^post16, ntStatus_8^0'=ntStatus_8^post16, lt_18^0'=lt_18^post16, __disjvr_1^0'=__disjvr_1^post16, (lt_13^0-lt_13^post16 == 0 /\ cnt_34^0-cnt_34^post16 == 0 /\ -Result_4^post16+Result_4^0 == 0 /\ lt_20^0-lt_20^post16 == 0 /\ lt_12^0-lt_12^post16 == 0 /\ -ntStatus_8^post16+ntStatus_8^0 == 0 /\ -MaximumInterfaceType_9^post16+MaximumInterfaceType_9^0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post16 == 0 /\ lt_14^0-lt_14^post16 == 0 /\ ct_15^0-ct_15^post16 == 0 /\ -ct_115^post16+ct_115^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post16 == 0 /\ -lt_19^post16+lt_19^0 == 0 /\ ct_64^0-ct_64^post16 == 0 /\ -__const_256^post16+__const_256^0 == 0 /\ -lt_18^post16+lt_18^0 == 0 /\ -fdoExtension_7^post16+fdoExtension_7^0 == 0 /\ -__disjvr_1^post16+__disjvr_1^0 == 0 /\ lt_17^0-lt_17^post16 == 0 /\ cnt_29^0-cnt_29^post16 == 0 /\ Dc_6^0-Dc_6^post16 == 0 /\ -__retres1_10^post16+__retres1_10^0 == 0 /\ lt_16^0-lt_16^post16 == 0 /\ __disjvr_0^0-__disjvr_0^post16 == 0), cost: 1


Applied preprocessing
Original rule:
l0 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post0, lt_14^0'=lt_14^post0, ct_15^0'=ct_15^post0, InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, cnt_29^0'=cnt_29^post0, lt_20^0'=lt_20^post0, lt_17^0'=lt_17^post0, __disjvr_0^0'=__disjvr_0^post0, Result_4^0'=Result_4^post0, lt_13^0'=lt_13^post0, ct_115^0'=ct_115^post0, lt_19^0'=lt_19^post0, Dc_6^0'=Dc_6^post0, __retres1_10^0'=__retres1_10^post0, __const_256^0'=__const_256^post0, lt_16^0'=lt_16^post0, ct_64^0'=ct_64^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, lt_12^0'=lt_12^post0, cnt_34^0'=cnt_34^post0, ntStatus_8^0'=ntStatus_8^post0, lt_18^0'=lt_18^post0, __disjvr_1^0'=__disjvr_1^post0, (0 == 0 /\ -lt_18^post0+lt_18^0 == 0 /\ __disjvr_0^0-__disjvr_0^post0 == 0 /\ lt_12^0-lt_12^post0 == 0 /\ -__disjvr_1^post0+__disjvr_1^0 == 0 /\ lt_13^0-lt_13^post0 == 0 /\ lt_17^0-lt_17^post0 == 0 /\ -cnt_34^post0+cnt_34^0 == 0 /\ lt_20^0-lt_20^post0 == 0 /\ -lt_19^post0+lt_19^0 == 0 /\ -Result_4^post0+Result_4^0 == 0 /\ -ct_64^post0+ct_64^0 == 0 /\ -__retres1_10^post0+__retres1_10^0 == 0 /\ lt_14^0-lt_14^post0 == 0 /\ ct_15^0-ct_15^post0 == 0 /\ lt_16^0-lt_16^post0 == 0 /\ cnt_29^0-cnt_29^post0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post0 == 0 /\ -__const_256^post0+__const_256^0 == 0 /\ -ct_115^post0+ct_115^0 == 0), cost: 1
New rule:
l0 -> l1 : InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, Dc_6^0'=Dc_6^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, ntStatus_8^0'=ntStatus_8^post0, 0 == 0, cost: 1

Applied preprocessing
Original rule:
l1 -> l2 : __cil_tmp2_11^0'=__cil_tmp2_11^post1, lt_14^0'=lt_14^post1, ct_15^0'=ct_15^post1, InterfaceType_5^0'=InterfaceType_5^post1, fdoExtension_7^0'=fdoExtension_7^post1, cnt_29^0'=cnt_29^post1, lt_20^0'=lt_20^post1, lt_17^0'=lt_17^post1, __disjvr_0^0'=__disjvr_0^post1, Result_4^0'=Result_4^post1, lt_13^0'=lt_13^post1, ct_115^0'=ct_115^post1, lt_19^0'=lt_19^post1, Dc_6^0'=Dc_6^post1, __retres1_10^0'=__retres1_10^post1, __const_256^0'=__const_256^post1, lt_16^0'=lt_16^post1, ct_64^0'=ct_64^post1, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post1, lt_12^0'=lt_12^post1, cnt_34^0'=cnt_34^post1, ntStatus_8^0'=ntStatus_8^post1, lt_18^0'=lt_18^post1, __disjvr_1^0'=__disjvr_1^post1, (0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post1 == 0 /\ lt_13^0-lt_13^post1 == 0 /\ -1+lt_16^10-cnt_29^0 == 0 /\ -ntStatus_8^post1+ntStatus_8^0 == 0 /\ 1+lt_16^10-lt_17^10 <= 0 /\ lt_17^10-cnt_34^0 == 0 /\ cnt_34^0-cnt_34^post1 == 0 /\ -lt_12^post1+lt_12^0 == 0 /\ -__retres1_10^post1+__retres1_10^0 == 0 /\ 1-lt_20^10+lt_19^10 <= 0 /\ lt_20^10-cnt_34^0 == 0 /\ -__const_256^post1+__const_256^0 == 0 /\ cnt_29^0-cnt_29^post1 == 0 /\ Dc_6^0-Dc_6^post1 == 0 /\ -cnt_29^0+lt_18^10 == 0 /\ -cnt_29^0+lt_19^10 == 0 /\ Result_4^0-Result_4^post1 == 0 /\ InterfaceType_5^0-InterfaceType_5^post1 == 0 /\ -ct_115^post1+ct_115^0 == 0 /\ ct_64^0-ct_64^post1 == 0 /\ -fdoExtension_7^post1+fdoExtension_7^0 == 0 /\ -ct_115^0+lt_14^10 == 0 /\ -__disjvr_1^post1+__disjvr_1^0 == 0 /\ -MaximumInterfaceType_9^post1+MaximumInterfaceType_9^0 == 0 /\ __disjvr_0^0-__disjvr_0^post1 == 0 /\ lt_14^10 <= 0), cost: 1
New rule:
l1 -> l2 : lt_14^0'=lt_14^post1, ct_15^0'=ct_15^post1, lt_20^0'=lt_20^post1, lt_17^0'=lt_17^post1, lt_19^0'=lt_19^post1, lt_16^0'=lt_16^post1, lt_18^0'=lt_18^post1, (ct_115^0 <= 0 /\ 2+cnt_29^0-cnt_34^0 <= 0), cost: 1

Applied preprocessing
Original rule:
l2 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post2, lt_14^0'=lt_14^post2, ct_15^0'=ct_15^post2, InterfaceType_5^0'=InterfaceType_5^post2, fdoExtension_7^0'=fdoExtension_7^post2, cnt_29^0'=cnt_29^post2, lt_20^0'=lt_20^post2, lt_17^0'=lt_17^post2, __disjvr_0^0'=__disjvr_0^post2, Result_4^0'=Result_4^post2, lt_13^0'=lt_13^post2, ct_115^0'=ct_115^post2, lt_19^0'=lt_19^post2, Dc_6^0'=Dc_6^post2, __retres1_10^0'=__retres1_10^post2, __const_256^0'=__const_256^post2, lt_16^0'=lt_16^post2, ct_64^0'=ct_64^post2, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post2, lt_12^0'=lt_12^post2, cnt_34^0'=cnt_34^post2, ntStatus_8^0'=ntStatus_8^post2, lt_18^0'=lt_18^post2, __disjvr_1^0'=__disjvr_1^post2, (ct_15^0-ct_15^post2 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post2 == 0 /\ -lt_12^post2+lt_12^0 == 0 /\ -lt_16^post2+lt_16^0 == 0 /\ lt_14^0-lt_14^post2 == 0 /\ MaximumInterfaceType_9^0-MaximumInterfaceType_9^post2 == 0 /\ -lt_13^post2+lt_13^0 == 0 /\ ct_115^0-ct_115^post2 == 0 /\ lt_17^0-lt_17^post2 == 0 /\ Result_4^0-Result_4^post2 == 0 /\ Dc_6^0-Dc_6^post2 == 0 /\ __disjvr_0^0-__disjvr_0^post2 == 0 /\ -cnt_34^post2+cnt_34^0 == 0 /\ -ntStatus_8^post2+ntStatus_8^0 == 0 /\ lt_20^0-lt_20^post2 == 0 /\ -cnt_29^post2+cnt_29^0 == 0 /\ -InterfaceType_5^post2+InterfaceType_5^0 == 0 /\ -__disjvr_1^post2+__disjvr_1^0 == 0 /\ -__const_256^post2+__const_256^0 == 0 /\ -__retres1_10^post2+__retres1_10^0 == 0 /\ lt_19^0-lt_19^post2 == 0 /\ fdoExtension_7^0-fdoExtension_7^post2 == 0 /\ -lt_18^post2+lt_18^0 == 0 /\ -ct_64^post2+ct_64^0 == 0), cost: 1
New rule:
l2 -> l1 : TRUE, cost: 1

Applied preprocessing
Original rule:
l1 -> l3 : __cil_tmp2_11^0'=__cil_tmp2_11^post3, lt_14^0'=lt_14^post3, ct_15^0'=ct_15^post3, InterfaceType_5^0'=InterfaceType_5^post3, fdoExtension_7^0'=fdoExtension_7^post3, cnt_29^0'=cnt_29^post3, lt_20^0'=lt_20^post3, lt_17^0'=lt_17^post3, __disjvr_0^0'=__disjvr_0^post3, Result_4^0'=Result_4^post3, lt_13^0'=lt_13^post3, ct_115^0'=ct_115^post3, lt_19^0'=lt_19^post3, Dc_6^0'=Dc_6^post3, __retres1_10^0'=__retres1_10^post3, __const_256^0'=__const_256^post3, lt_16^0'=lt_16^post3, ct_64^0'=ct_64^post3, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post3, lt_12^0'=lt_12^post3, cnt_34^0'=cnt_34^post3, ntStatus_8^0'=ntStatus_8^post3, lt_18^0'=lt_18^post3, __disjvr_1^0'=__disjvr_1^post3, (0 == 0 /\ -__disjvr_0^post3+__disjvr_0^0 == 0 /\ -__const_256^0+lt_13^10 <= 0 /\ -1+lt_16^110-cnt_29^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post3 == 0 /\ -__retres1_10^post3+__retres1_10^0 == 0 /\ Result_4^0-Result_4^post3 == 0 /\ -ntStatus_8^post3+ntStatus_8^0 == 0 /\ -cnt_34^0+lt_17^110 == 0 /\ 1+lt_16^110-lt_17^110 <= 0 /\ __const_256^0-lt_13^10 <= 0 /\ -Dc_6^post3+Dc_6^0 == 0 /\ lt_18^110-cnt_29^0 == 0 /\ -ct_115^0+lt_13^10 == 0 /\ 1-lt_14^110 <= 0 /\ -ct_64^post3+ct_64^0 == 0 /\ 1-lt_20^110+lt_19^110 <= 0 /\ -__const_256^post3+__const_256^0 == 0 /\ -ct_115^post3+ct_115^0 == 0 /\ -lt_12^post3+lt_12^0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post3 == 0 /\ -ct_115^0+lt_14^110 == 0 /\ -cnt_34^post3+cnt_34^0 == 0 /\ lt_20^110-cnt_34^0 == 0 /\ -__disjvr_1^post3+__disjvr_1^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post3 == 0 /\ -MaximumInterfaceType_9^post3+MaximumInterfaceType_9^0 == 0 /\ -cnt_29^0+lt_19^110 == 0 /\ cnt_29^0-cnt_29^post3 == 0), cost: 1
New rule:
l1 -> l3 : lt_14^0'=lt_14^post3, ct_15^0'=ct_15^post3, lt_20^0'=lt_20^post3, lt_17^0'=lt_17^post3, lt_13^0'=lt_13^post3, lt_19^0'=lt_19^post3, lt_16^0'=lt_16^post3, lt_18^0'=lt_18^post3, (-1+ct_115^0 >= 0 /\ -ct_115^0+__const_256^0 == 0 /\ 2+cnt_29^0-cnt_34^0 <= 0), cost: 1

Applied preprocessing
Original rule:
l3 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post4, lt_14^0'=lt_14^post4, ct_15^0'=ct_15^post4, InterfaceType_5^0'=InterfaceType_5^post4, fdoExtension_7^0'=fdoExtension_7^post4, cnt_29^0'=cnt_29^post4, lt_20^0'=lt_20^post4, lt_17^0'=lt_17^post4, __disjvr_0^0'=__disjvr_0^post4, Result_4^0'=Result_4^post4, lt_13^0'=lt_13^post4, ct_115^0'=ct_115^post4, lt_19^0'=lt_19^post4, Dc_6^0'=Dc_6^post4, __retres1_10^0'=__retres1_10^post4, __const_256^0'=__const_256^post4, lt_16^0'=lt_16^post4, ct_64^0'=ct_64^post4, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post4, lt_12^0'=lt_12^post4, cnt_34^0'=cnt_34^post4, ntStatus_8^0'=ntStatus_8^post4, lt_18^0'=lt_18^post4, __disjvr_1^0'=__disjvr_1^post4, (-MaximumInterfaceType_9^post4+MaximumInterfaceType_9^0 == 0 /\ __disjvr_0^0-__disjvr_0^post4 == 0 /\ lt_12^0-lt_12^post4 == 0 /\ -lt_18^post4+lt_18^0 == 0 /\ -__disjvr_1^post4+__disjvr_1^0 == 0 /\ lt_17^0-lt_17^post4 == 0 /\ -fdoExtension_7^post4+fdoExtension_7^0 == 0 /\ lt_20^0-lt_20^post4 == 0 /\ -cnt_34^post4+cnt_34^0 == 0 /\ -lt_19^post4+lt_19^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post4 == 0 /\ -ntStatus_8^post4+ntStatus_8^0 == 0 /\ lt_14^0-lt_14^post4 == 0 /\ ct_15^0-ct_15^post4 == 0 /\ -__retres1_10^post4+__retres1_10^0 == 0 /\ -ct_64^post4+ct_64^0 == 0 /\ cnt_29^0-cnt_29^post4 == 0 /\ Dc_6^0-Dc_6^post4 == 0 /\ lt_16^0-lt_16^post4 == 0 /\ lt_13^0-lt_13^post4 == 0 /\ Result_4^0-Result_4^post4 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post4 == 0 /\ -__const_256^post4+__const_256^0 == 0 /\ -ct_115^post4+ct_115^0 == 0), cost: 1
New rule:
l3 -> l1 : TRUE, cost: 1

Applied preprocessing
Original rule:
l1 -> l4 : __cil_tmp2_11^0'=__cil_tmp2_11^post5, lt_14^0'=lt_14^post5, ct_15^0'=ct_15^post5, InterfaceType_5^0'=InterfaceType_5^post5, fdoExtension_7^0'=fdoExtension_7^post5, cnt_29^0'=cnt_29^post5, lt_20^0'=lt_20^post5, lt_17^0'=lt_17^post5, __disjvr_0^0'=__disjvr_0^post5, Result_4^0'=Result_4^post5, lt_13^0'=lt_13^post5, ct_115^0'=ct_115^post5, lt_19^0'=lt_19^post5, Dc_6^0'=Dc_6^post5, __retres1_10^0'=__retres1_10^post5, __const_256^0'=__const_256^post5, lt_16^0'=lt_16^post5, ct_64^0'=ct_64^post5, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post5, lt_12^0'=lt_12^post5, cnt_34^0'=cnt_34^post5, ntStatus_8^0'=ntStatus_8^post5, lt_18^0'=lt_18^post5, __disjvr_1^0'=__disjvr_1^post5, (0 == 0 /\ -__retres1_10^post5+__retres1_10^0 == 0 /\ -lt_12^post5+lt_12^0 == 0 /\ -ntStatus_8^post5+ntStatus_8^0 == 0 /\ lt_17^120-lt_16^120 <= 0 /\ ct_64^0-ct_64^post5 == 0 /\ -1-cnt_29^0+lt_16^120 == 0 /\ -cnt_29^0+lt_19^120 == 0 /\ InterfaceType_5^0-InterfaceType_5^post5 == 0 /\ -MaximumInterfaceType_9^post5+MaximumInterfaceType_9^0 == 0 /\ lt_17^120-cnt_34^0 == 0 /\ lt_20^120-cnt_34^0 == 0 /\ -Dc_6^post5+Dc_6^0 == 0 /\ -lt_13^post5+lt_13^0 == 0 /\ cnt_29^0-cnt_29^post5 == 0 /\ 1-lt_20^120+lt_19^120 <= 0 /\ Result_4^0-Result_4^post5 == 0 /\ -ct_64^0+lt_14^120 == 0 /\ -ct_115^post5+ct_115^0 == 0 /\ lt_14^120 <= 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post5 == 0 /\ -__disjvr_0^post5+__disjvr_0^0 == 0 /\ -cnt_34^post5+cnt_34^0 == 0 /\ -cnt_29^0+lt_18^120 == 0 /\ -__disjvr_1^post5+__disjvr_1^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post5 == 0 /\ __const_256^0-__const_256^post5 == 0), cost: 1
New rule:
l1 -> l4 : lt_14^0'=lt_14^post5, ct_15^0'=ct_15^post5, lt_20^0'=lt_20^post5, lt_17^0'=lt_17^post5, lt_19^0'=lt_19^post5, lt_16^0'=lt_16^post5, lt_18^0'=lt_18^post5, (-1-cnt_29^0+cnt_34^0 == 0 /\ ct_64^0 <= 0), cost: 1

Applied preprocessing
Original rule:
l4 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post6, lt_14^0'=lt_14^post6, ct_15^0'=ct_15^post6, InterfaceType_5^0'=InterfaceType_5^post6, fdoExtension_7^0'=fdoExtension_7^post6, cnt_29^0'=cnt_29^post6, lt_20^0'=lt_20^post6, lt_17^0'=lt_17^post6, __disjvr_0^0'=__disjvr_0^post6, Result_4^0'=Result_4^post6, lt_13^0'=lt_13^post6, ct_115^0'=ct_115^post6, lt_19^0'=lt_19^post6, Dc_6^0'=Dc_6^post6, __retres1_10^0'=__retres1_10^post6, __const_256^0'=__const_256^post6, lt_16^0'=lt_16^post6, ct_64^0'=ct_64^post6, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post6, lt_12^0'=lt_12^post6, cnt_34^0'=cnt_34^post6, ntStatus_8^0'=ntStatus_8^post6, lt_18^0'=lt_18^post6, __disjvr_1^0'=__disjvr_1^post6, (lt_13^0-lt_13^post6 == 0 /\ cnt_34^0-cnt_34^post6 == 0 /\ -Result_4^post6+Result_4^0 == 0 /\ -lt_19^post6+lt_19^0 == 0 /\ lt_20^0-lt_20^post6 == 0 /\ lt_12^0-lt_12^post6 == 0 /\ -ntStatus_8^post6+ntStatus_8^0 == 0 /\ -MaximumInterfaceType_9^post6+MaximumInterfaceType_9^0 == 0 /\ ct_15^0-ct_15^post6 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post6 == 0 /\ -ct_115^post6+ct_115^0 == 0 /\ lt_14^0-lt_14^post6 == 0 /\ InterfaceType_5^0-InterfaceType_5^post6 == 0 /\ -__const_256^post6+__const_256^0 == 0 /\ ct_64^0-ct_64^post6 == 0 /\ lt_17^0-lt_17^post6 == 0 /\ -fdoExtension_7^post6+fdoExtension_7^0 == 0 /\ -lt_18^post6+lt_18^0 == 0 /\ -__disjvr_1^post6+__disjvr_1^0 == 0 /\ -__retres1_10^post6+__retres1_10^0 == 0 /\ Dc_6^0-Dc_6^post6 == 0 /\ cnt_29^0-cnt_29^post6 == 0 /\ lt_16^0-lt_16^post6 == 0 /\ __disjvr_0^0-__disjvr_0^post6 == 0), cost: 1
New rule:
l4 -> l1 : TRUE, cost: 1

Applied preprocessing
Original rule:
l1 -> l5 : __cil_tmp2_11^0'=__cil_tmp2_11^post7, lt_14^0'=lt_14^post7, ct_15^0'=ct_15^post7, InterfaceType_5^0'=InterfaceType_5^post7, fdoExtension_7^0'=fdoExtension_7^post7, cnt_29^0'=cnt_29^post7, lt_20^0'=lt_20^post7, lt_17^0'=lt_17^post7, __disjvr_0^0'=__disjvr_0^post7, Result_4^0'=Result_4^post7, lt_13^0'=lt_13^post7, ct_115^0'=ct_115^post7, lt_19^0'=lt_19^post7, Dc_6^0'=Dc_6^post7, __retres1_10^0'=__retres1_10^post7, __const_256^0'=__const_256^post7, lt_16^0'=lt_16^post7, ct_64^0'=ct_64^post7, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post7, lt_12^0'=lt_12^post7, cnt_34^0'=cnt_34^post7, ntStatus_8^0'=ntStatus_8^post7, lt_18^0'=lt_18^post7, __disjvr_1^0'=__disjvr_1^post7, (0 == 0 /\ cnt_29^0-cnt_29^post7 == 0 /\ -__const_256^0+lt_13^110 <= 0 /\ -Result_4^post7+Result_4^0 == 0 /\ Dc_6^0-Dc_6^post7 == 0 /\ lt_17^130-lt_16^130 <= 0 /\ -1-cnt_29^0+lt_16^130 == 0 /\ -ntStatus_8^post7+ntStatus_8^0 == 0 /\ -lt_12^post7+lt_12^0 == 0 /\ __retres1_10^0-__retres1_10^post7 == 0 /\ lt_13^110-ct_64^0 == 0 /\ lt_17^130-cnt_34^0 == 0 /\ __const_256^0-lt_13^110 <= 0 /\ ct_115^0-ct_115^post7 == 0 /\ __const_256^0-__const_256^post7 == 0 /\ InterfaceType_5^0-InterfaceType_5^post7 == 0 /\ -MaximumInterfaceType_9^post7+MaximumInterfaceType_9^0 == 0 /\ -__disjvr_0^post7+__disjvr_0^0 == 0 /\ lt_18^130-cnt_29^0 == 0 /\ ct_64^0-ct_64^post7 == 0 /\ lt_14^130-ct_64^0 == 0 /\ -cnt_34^post7+cnt_34^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post7 == 0 /\ -__cil_tmp2_11^post7+__cil_tmp2_11^0 == 0 /\ -cnt_29^0+lt_19^130 == 0 /\ -__disjvr_1^post7+__disjvr_1^0 == 0 /\ 1-lt_14^130 <= 0 /\ 1-lt_20^130+lt_19^130 <= 0 /\ lt_20^130-cnt_34^0 == 0), cost: 1
New rule:
l1 -> l5 : lt_14^0'=lt_14^post7, ct_15^0'=ct_15^post7, lt_20^0'=lt_20^post7, lt_17^0'=lt_17^post7, lt_13^0'=lt_13^post7, lt_19^0'=lt_19^post7, lt_16^0'=lt_16^post7, lt_18^0'=lt_18^post7, (-1-cnt_29^0+cnt_34^0 == 0 /\ __const_256^0-ct_64^0 == 0 /\ 1-ct_64^0 <= 0), cost: 1

Applied preprocessing
Original rule:
l5 -> l1 : __cil_tmp2_11^0'=__cil_tmp2_11^post8, lt_14^0'=lt_14^post8, ct_15^0'=ct_15^post8, InterfaceType_5^0'=InterfaceType_5^post8, fdoExtension_7^0'=fdoExtension_7^post8, cnt_29^0'=cnt_29^post8, lt_20^0'=lt_20^post8, lt_17^0'=lt_17^post8, __disjvr_0^0'=__disjvr_0^post8, Result_4^0'=Result_4^post8, lt_13^0'=lt_13^post8, ct_115^0'=ct_115^post8, lt_19^0'=lt_19^post8, Dc_6^0'=Dc_6^post8, __retres1_10^0'=__retres1_10^post8, __const_256^0'=__const_256^post8, lt_16^0'=lt_16^post8, ct_64^0'=ct_64^post8, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post8, lt_12^0'=lt_12^post8, cnt_34^0'=cnt_34^post8, ntStatus_8^0'=ntStatus_8^post8, lt_18^0'=lt_18^post8, __disjvr_1^0'=__disjvr_1^post8, (-__retres1_10^post8+__retres1_10^0 == 0 /\ -lt_16^post8+lt_16^0 == 0 /\ cnt_29^0-cnt_29^post8 == 0 /\ -ct_64^post8+ct_64^0 == 0 /\ lt_20^0-lt_20^post8 == 0 /\ -lt_12^post8+lt_12^0 == 0 /\ -Dc_6^post8+Dc_6^0 == 0 /\ -ntStatus_8^post8+ntStatus_8^0 == 0 /\ -lt_13^post8+lt_13^0 == 0 /\ -MaximumInterfaceType_9^post8+MaximumInterfaceType_9^0 == 0 /\ fdoExtension_7^0-fdoExtension_7^post8 == 0 /\ lt_14^0-lt_14^post8 == 0 /\ __const_256^0-__const_256^post8 == 0 /\ ct_115^0-ct_115^post8 == 0 /\ -cnt_34^post8+cnt_34^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post8 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post8 == 0 /\ Result_4^0-Result_4^post8 == 0 /\ lt_19^0-lt_19^post8 == 0 /\ __disjvr_0^0-__disjvr_0^post8 == 0 /\ -lt_17^post8+lt_17^0 == 0 /\ ct_15^0-ct_15^post8 == 0 /\ -__disjvr_1^post8+__disjvr_1^0 == 0 /\ lt_18^0-lt_18^post8 == 0), cost: 1
New rule:
l5 -> l1 : TRUE, cost: 1

Applied preprocessing
Original rule:
l12 -> l0 : __cil_tmp2_11^0'=__cil_tmp2_11^post16, lt_14^0'=lt_14^post16, ct_15^0'=ct_15^post16, InterfaceType_5^0'=InterfaceType_5^post16, fdoExtension_7^0'=fdoExtension_7^post16, cnt_29^0'=cnt_29^post16, lt_20^0'=lt_20^post16, lt_17^0'=lt_17^post16, __disjvr_0^0'=__disjvr_0^post16, Result_4^0'=Result_4^post16, lt_13^0'=lt_13^post16, ct_115^0'=ct_115^post16, lt_19^0'=lt_19^post16, Dc_6^0'=Dc_6^post16, __retres1_10^0'=__retres1_10^post16, __const_256^0'=__const_256^post16, lt_16^0'=lt_16^post16, ct_64^0'=ct_64^post16, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post16, lt_12^0'=lt_12^post16, cnt_34^0'=cnt_34^post16, ntStatus_8^0'=ntStatus_8^post16, lt_18^0'=lt_18^post16, __disjvr_1^0'=__disjvr_1^post16, (lt_13^0-lt_13^post16 == 0 /\ cnt_34^0-cnt_34^post16 == 0 /\ -Result_4^post16+Result_4^0 == 0 /\ lt_20^0-lt_20^post16 == 0 /\ lt_12^0-lt_12^post16 == 0 /\ -ntStatus_8^post16+ntStatus_8^0 == 0 /\ -MaximumInterfaceType_9^post16+MaximumInterfaceType_9^0 == 0 /\ __cil_tmp2_11^0-__cil_tmp2_11^post16 == 0 /\ lt_14^0-lt_14^post16 == 0 /\ ct_15^0-ct_15^post16 == 0 /\ -ct_115^post16+ct_115^0 == 0 /\ InterfaceType_5^0-InterfaceType_5^post16 == 0 /\ -lt_19^post16+lt_19^0 == 0 /\ ct_64^0-ct_64^post16 == 0 /\ -__const_256^post16+__const_256^0 == 0 /\ -lt_18^post16+lt_18^0 == 0 /\ -fdoExtension_7^post16+fdoExtension_7^0 == 0 /\ -__disjvr_1^post16+__disjvr_1^0 == 0 /\ lt_17^0-lt_17^post16 == 0 /\ cnt_29^0-cnt_29^post16 == 0 /\ Dc_6^0-Dc_6^post16 == 0 /\ -__retres1_10^post16+__retres1_10^0 == 0 /\ lt_16^0-lt_16^post16 == 0 /\ __disjvr_0^0-__disjvr_0^post16 == 0), cost: 1
New rule:
l12 -> l0 : TRUE, cost: 1

Simplified rules
Start location: l12
  17: l0 -> l1 : InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, Dc_6^0'=Dc_6^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, ntStatus_8^0'=ntStatus_8^post0, 0 == 0, cost: 1
  18: l1 -> l2 : lt_14^0'=lt_14^post1, ct_15^0'=ct_15^post1, lt_20^0'=lt_20^post1, lt_17^0'=lt_17^post1, lt_19^0'=lt_19^post1, lt_16^0'=lt_16^post1, lt_18^0'=lt_18^post1, (ct_115^0 <= 0 /\ 2+cnt_29^0-cnt_34^0 <= 0), cost: 1
  20: l1 -> l3 : lt_14^0'=lt_14^post3, ct_15^0'=ct_15^post3, lt_20^0'=lt_20^post3, lt_17^0'=lt_17^post3, lt_13^0'=lt_13^post3, lt_19^0'=lt_19^post3, lt_16^0'=lt_16^post3, lt_18^0'=lt_18^post3, (-1+ct_115^0 >= 0 /\ -ct_115^0+__const_256^0 == 0 /\ 2+cnt_29^0-cnt_34^0 <= 0), cost: 1
  22: l1 -> l4 : lt_14^0'=lt_14^post5, ct_15^0'=ct_15^post5, lt_20^0'=lt_20^post5, lt_17^0'=lt_17^post5, lt_19^0'=lt_19^post5, lt_16^0'=lt_16^post5, lt_18^0'=lt_18^post5, (-1-cnt_29^0+cnt_34^0 == 0 /\ ct_64^0 <= 0), cost: 1
  24: l1 -> l5 : lt_14^0'=lt_14^post7, ct_15^0'=ct_15^post7, lt_20^0'=lt_20^post7, lt_17^0'=lt_17^post7, lt_13^0'=lt_13^post7, lt_19^0'=lt_19^post7, lt_16^0'=lt_16^post7, lt_18^0'=lt_18^post7, (-1-cnt_29^0+cnt_34^0 == 0 /\ __const_256^0-ct_64^0 == 0 /\ 1-ct_64^0 <= 0), cost: 1
  19: l2 -> l1 : TRUE, cost: 1
  21: l3 -> l1 : TRUE, cost: 1
  23: l4 -> l1 : TRUE, cost: 1
  25: l5 -> l1 : TRUE, cost: 1
  26: l12 -> l0 : TRUE, cost: 1


Eliminating location l0 by chaining:

Applied chaining
First rule:
l12 -> l0 : TRUE, cost: 1
Second rule:
l0 -> l1 : InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, Dc_6^0'=Dc_6^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, ntStatus_8^0'=ntStatus_8^post0, 0 == 0, cost: 1
New rule:
l12 -> l1 : InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, Dc_6^0'=Dc_6^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, ntStatus_8^0'=ntStatus_8^post0, 0 == 0, cost: 2

Applied deletion
Removed the following rules: 17 26

Eliminating location l2 by chaining:

Applied chaining
First rule:
l1 -> l2 : lt_14^0'=lt_14^post1, ct_15^0'=ct_15^post1, lt_20^0'=lt_20^post1, lt_17^0'=lt_17^post1, lt_19^0'=lt_19^post1, lt_16^0'=lt_16^post1, lt_18^0'=lt_18^post1, (ct_115^0 <= 0 /\ 2+cnt_29^0-cnt_34^0 <= 0), cost: 1
Second rule:
l2 -> l1 : TRUE, cost: 1
New rule:
l1 -> l1 : lt_14^0'=lt_14^post1, ct_15^0'=ct_15^post1, lt_20^0'=lt_20^post1, lt_17^0'=lt_17^post1, lt_19^0'=lt_19^post1, lt_16^0'=lt_16^post1, lt_18^0'=lt_18^post1, (ct_115^0 <= 0 /\ 2+cnt_29^0-cnt_34^0 <= 0), cost: 2

Applied deletion
Removed the following rules: 18 19

Eliminating location l3 by chaining:

Applied chaining
First rule:
l1 -> l3 : lt_14^0'=lt_14^post3, ct_15^0'=ct_15^post3, lt_20^0'=lt_20^post3, lt_17^0'=lt_17^post3, lt_13^0'=lt_13^post3, lt_19^0'=lt_19^post3, lt_16^0'=lt_16^post3, lt_18^0'=lt_18^post3, (-1+ct_115^0 >= 0 /\ -ct_115^0+__const_256^0 == 0 /\ 2+cnt_29^0-cnt_34^0 <= 0), cost: 1
Second rule:
l3 -> l1 : TRUE, cost: 1
New rule:
l1 -> l1 : lt_14^0'=lt_14^post3, ct_15^0'=ct_15^post3, lt_20^0'=lt_20^post3, lt_17^0'=lt_17^post3, lt_13^0'=lt_13^post3, lt_19^0'=lt_19^post3, lt_16^0'=lt_16^post3, lt_18^0'=lt_18^post3, (-1+ct_115^0 >= 0 /\ -ct_115^0+__const_256^0 == 0 /\ 2+cnt_29^0-cnt_34^0 <= 0), cost: 2

Applied deletion
Removed the following rules: 20 21

Eliminating location l4 by chaining:

Applied chaining
First rule:
l1 -> l4 : lt_14^0'=lt_14^post5, ct_15^0'=ct_15^post5, lt_20^0'=lt_20^post5, lt_17^0'=lt_17^post5, lt_19^0'=lt_19^post5, lt_16^0'=lt_16^post5, lt_18^0'=lt_18^post5, (-1-cnt_29^0+cnt_34^0 == 0 /\ ct_64^0 <= 0), cost: 1
Second rule:
l4 -> l1 : TRUE, cost: 1
New rule:
l1 -> l1 : lt_14^0'=lt_14^post5, ct_15^0'=ct_15^post5, lt_20^0'=lt_20^post5, lt_17^0'=lt_17^post5, lt_19^0'=lt_19^post5, lt_16^0'=lt_16^post5, lt_18^0'=lt_18^post5, (-1-cnt_29^0+cnt_34^0 == 0 /\ ct_64^0 <= 0), cost: 2

Applied deletion
Removed the following rules: 22 23

Eliminating location l5 by chaining:

Applied chaining
First rule:
l1 -> l5 : lt_14^0'=lt_14^post7, ct_15^0'=ct_15^post7, lt_20^0'=lt_20^post7, lt_17^0'=lt_17^post7, lt_13^0'=lt_13^post7, lt_19^0'=lt_19^post7, lt_16^0'=lt_16^post7, lt_18^0'=lt_18^post7, (-1-cnt_29^0+cnt_34^0 == 0 /\ __const_256^0-ct_64^0 == 0 /\ 1-ct_64^0 <= 0), cost: 1
Second rule:
l5 -> l1 : TRUE, cost: 1
New rule:
l1 -> l1 : lt_14^0'=lt_14^post7, ct_15^0'=ct_15^post7, lt_20^0'=lt_20^post7, lt_17^0'=lt_17^post7, lt_13^0'=lt_13^post7, lt_19^0'=lt_19^post7, lt_16^0'=lt_16^post7, lt_18^0'=lt_18^post7, (-1-cnt_29^0+cnt_34^0 == 0 /\ __const_256^0-ct_64^0 == 0 /\ 1-ct_64^0 <= 0), cost: 2

Applied deletion
Removed the following rules: 24 25

Eliminated locations on linear paths
Start location: l12
  28: l1 -> l1 : lt_14^0'=lt_14^post1, ct_15^0'=ct_15^post1, lt_20^0'=lt_20^post1, lt_17^0'=lt_17^post1, lt_19^0'=lt_19^post1, lt_16^0'=lt_16^post1, lt_18^0'=lt_18^post1, (ct_115^0 <= 0 /\ 2+cnt_29^0-cnt_34^0 <= 0), cost: 2
  29: l1 -> l1 : lt_14^0'=lt_14^post3, ct_15^0'=ct_15^post3, lt_20^0'=lt_20^post3, lt_17^0'=lt_17^post3, lt_13^0'=lt_13^post3, lt_19^0'=lt_19^post3, lt_16^0'=lt_16^post3, lt_18^0'=lt_18^post3, (-1+ct_115^0 >= 0 /\ -ct_115^0+__const_256^0 == 0 /\ 2+cnt_29^0-cnt_34^0 <= 0), cost: 2
  30: l1 -> l1 : lt_14^0'=lt_14^post5, ct_15^0'=ct_15^post5, lt_20^0'=lt_20^post5, lt_17^0'=lt_17^post5, lt_19^0'=lt_19^post5, lt_16^0'=lt_16^post5, lt_18^0'=lt_18^post5, (-1-cnt_29^0+cnt_34^0 == 0 /\ ct_64^0 <= 0), cost: 2
  31: l1 -> l1 : lt_14^0'=lt_14^post7, ct_15^0'=ct_15^post7, lt_20^0'=lt_20^post7, lt_17^0'=lt_17^post7, lt_13^0'=lt_13^post7, lt_19^0'=lt_19^post7, lt_16^0'=lt_16^post7, lt_18^0'=lt_18^post7, (-1-cnt_29^0+cnt_34^0 == 0 /\ __const_256^0-ct_64^0 == 0 /\ 1-ct_64^0 <= 0), cost: 2
  27: l12 -> l1 : InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, Dc_6^0'=Dc_6^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, ntStatus_8^0'=ntStatus_8^post0, 0 == 0, cost: 2


Applied nonterm
Original rule:
l1 -> l1 : lt_14^0'=lt_14^post1, ct_15^0'=ct_15^post1, lt_20^0'=lt_20^post1, lt_17^0'=lt_17^post1, lt_19^0'=lt_19^post1, lt_16^0'=lt_16^post1, lt_18^0'=lt_18^post1, (ct_115^0 <= 0 /\ 2+cnt_29^0-cnt_34^0 <= 0), cost: 2
New rule:
l1 -> [13] : (-ct_115^0 >= 0 /\ -1+n >= 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM
Sub-proof via acceration calculus written to file:///tmp/tmpnam_HloGpc.txt

Applied nonterm
Original rule:
l1 -> l1 : lt_14^0'=lt_14^post3, ct_15^0'=ct_15^post3, lt_20^0'=lt_20^post3, lt_17^0'=lt_17^post3, lt_13^0'=lt_13^post3, lt_19^0'=lt_19^post3, lt_16^0'=lt_16^post3, lt_18^0'=lt_18^post3, (-1+ct_115^0 >= 0 /\ -ct_115^0+__const_256^0 == 0 /\ 2+cnt_29^0-cnt_34^0 <= 0), cost: 2
New rule:
l1 -> [13] : (-1+ct_115^0 >= 0 /\ -1+n0 >= 0 /\ ct_115^0-__const_256^0 >= 0 /\ -ct_115^0+__const_256^0 >= 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM
Sub-proof via acceration calculus written to file:///tmp/tmpnam_cKGejB.txt

Applied nonterm
Original rule:
l1 -> l1 : lt_14^0'=lt_14^post5, ct_15^0'=ct_15^post5, lt_20^0'=lt_20^post5, lt_17^0'=lt_17^post5, lt_19^0'=lt_19^post5, lt_16^0'=lt_16^post5, lt_18^0'=lt_18^post5, (-1-cnt_29^0+cnt_34^0 == 0 /\ ct_64^0 <= 0), cost: 2
New rule:
l1 -> [13] : (-1-cnt_29^0+cnt_34^0 >= 0 /\ -1+n1 >= 0 /\ -ct_64^0 >= 0 /\ 1+cnt_29^0-cnt_34^0 >= 0), cost: NONTERM
Sub-proof via acceration calculus written to file:///tmp/tmpnam_lkgPlC.txt

Applied nonterm
Original rule:
l1 -> l1 : lt_14^0'=lt_14^post7, ct_15^0'=ct_15^post7, lt_20^0'=lt_20^post7, lt_17^0'=lt_17^post7, lt_13^0'=lt_13^post7, lt_19^0'=lt_19^post7, lt_16^0'=lt_16^post7, lt_18^0'=lt_18^post7, (-1-cnt_29^0+cnt_34^0 == 0 /\ __const_256^0-ct_64^0 == 0 /\ 1-ct_64^0 <= 0), cost: 2
New rule:
l1 -> [13] : (-__const_256^0+ct_64^0 >= 0 /\ -1-cnt_29^0+cnt_34^0 >= 0 /\ __const_256^0-ct_64^0 >= 0 /\ -1+n2 >= 0 /\ -1+ct_64^0 >= 0 /\ 1+cnt_29^0-cnt_34^0 >= 0), cost: NONTERM
Sub-proof via acceration calculus written to file:///tmp/tmpnam_hGDECk.txt

Applied simplification
Original rule:
l1 -> [13] : (-ct_115^0 >= 0 /\ -1+n >= 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM
New rule:
l1 -> [13] : (ct_115^0 <= 0 /\ -1+n >= 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM

Applied simplification
Original rule:
l1 -> [13] : (-1-cnt_29^0+cnt_34^0 >= 0 /\ -1+n1 >= 0 /\ -ct_64^0 >= 0 /\ 1+cnt_29^0-cnt_34^0 >= 0), cost: NONTERM
New rule:
l1 -> [13] : (-1-cnt_29^0+cnt_34^0 >= 0 /\ -1+n1 >= 0 /\ ct_64^0 <= 0 /\ 1+cnt_29^0-cnt_34^0 >= 0), cost: NONTERM

Applied deletion
Removed the following rules: 28 29 30 31

Accelerated simple loops
Start location: l12
  33: l1 -> [13] : (-1+ct_115^0 >= 0 /\ -1+n0 >= 0 /\ ct_115^0-__const_256^0 >= 0 /\ -ct_115^0+__const_256^0 >= 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM
  35: l1 -> [13] : (-__const_256^0+ct_64^0 >= 0 /\ -1-cnt_29^0+cnt_34^0 >= 0 /\ __const_256^0-ct_64^0 >= 0 /\ -1+n2 >= 0 /\ -1+ct_64^0 >= 0 /\ 1+cnt_29^0-cnt_34^0 >= 0), cost: NONTERM
  36: l1 -> [13] : (ct_115^0 <= 0 /\ -1+n >= 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM
  37: l1 -> [13] : (-1-cnt_29^0+cnt_34^0 >= 0 /\ -1+n1 >= 0 /\ ct_64^0 <= 0 /\ 1+cnt_29^0-cnt_34^0 >= 0), cost: NONTERM
  27: l12 -> l1 : InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, Dc_6^0'=Dc_6^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, ntStatus_8^0'=ntStatus_8^post0, 0 == 0, cost: 2


Applied chaining
First rule:
l12 -> l1 : InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, Dc_6^0'=Dc_6^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, ntStatus_8^0'=ntStatus_8^post0, 0 == 0, cost: 2
Second rule:
l1 -> [13] : (-1+ct_115^0 >= 0 /\ -1+n0 >= 0 /\ ct_115^0-__const_256^0 >= 0 /\ -ct_115^0+__const_256^0 >= 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM
New rule:
l12 -> [13] : (-1+ct_115^0 >= 0 /\ -ct_115^0+__const_256^0 == 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM

Applied chaining
First rule:
l12 -> l1 : InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, Dc_6^0'=Dc_6^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, ntStatus_8^0'=ntStatus_8^post0, 0 == 0, cost: 2
Second rule:
l1 -> [13] : (-__const_256^0+ct_64^0 >= 0 /\ -1-cnt_29^0+cnt_34^0 >= 0 /\ __const_256^0-ct_64^0 >= 0 /\ -1+n2 >= 0 /\ -1+ct_64^0 >= 0 /\ 1+cnt_29^0-cnt_34^0 >= 0), cost: NONTERM
New rule:
l12 -> [13] : (__const_256^0-ct_64^0 == 0 /\ -1+ct_64^0 >= 0 /\ 1+cnt_29^0-cnt_34^0 == 0), cost: NONTERM

Applied chaining
First rule:
l12 -> l1 : InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, Dc_6^0'=Dc_6^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, ntStatus_8^0'=ntStatus_8^post0, 0 == 0, cost: 2
Second rule:
l1 -> [13] : (ct_115^0 <= 0 /\ -1+n >= 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM
New rule:
l12 -> [13] : (ct_115^0 <= 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM

Applied chaining
First rule:
l12 -> l1 : InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, Dc_6^0'=Dc_6^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, ntStatus_8^0'=ntStatus_8^post0, 0 == 0, cost: 2
Second rule:
l1 -> [13] : (-1-cnt_29^0+cnt_34^0 >= 0 /\ -1+n1 >= 0 /\ ct_64^0 <= 0 /\ 1+cnt_29^0-cnt_34^0 >= 0), cost: NONTERM
New rule:
l12 -> [13] : (ct_64^0 <= 0 /\ 1+cnt_29^0-cnt_34^0 == 0), cost: NONTERM

Applied deletion
Removed the following rules: 33 35 36 37

Chained accelerated rules with incoming rules
Start location: l12
  27: l12 -> l1 : InterfaceType_5^0'=InterfaceType_5^post0, fdoExtension_7^0'=fdoExtension_7^post0, Dc_6^0'=Dc_6^post0, MaximumInterfaceType_9^0'=MaximumInterfaceType_9^post0, ntStatus_8^0'=ntStatus_8^post0, 0 == 0, cost: 2
  38: l12 -> [13] : (-1+ct_115^0 >= 0 /\ -ct_115^0+__const_256^0 == 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM
  39: l12 -> [13] : (__const_256^0-ct_64^0 == 0 /\ -1+ct_64^0 >= 0 /\ 1+cnt_29^0-cnt_34^0 == 0), cost: NONTERM
  40: l12 -> [13] : (ct_115^0 <= 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM
  41: l12 -> [13] : (ct_64^0 <= 0 /\ 1+cnt_29^0-cnt_34^0 == 0), cost: NONTERM


Removed unreachable locations and irrelevant leafs
Start location: l12
  38: l12 -> [13] : (-1+ct_115^0 >= 0 /\ -ct_115^0+__const_256^0 == 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM
  39: l12 -> [13] : (__const_256^0-ct_64^0 == 0 /\ -1+ct_64^0 >= 0 /\ 1+cnt_29^0-cnt_34^0 == 0), cost: NONTERM
  40: l12 -> [13] : (ct_115^0 <= 0 /\ -2-cnt_29^0+cnt_34^0 >= 0), cost: NONTERM
  41: l12 -> [13] : (ct_64^0 <= 0 /\ 1+cnt_29^0-cnt_34^0 == 0), cost: NONTERM


Computing asymptotic complexity
Proved nontermination of rule 38 via SMT.

Proved the following lower bound
Complexity:  Nonterm
Cpx degree: Nonterm

Solved cost: NONTERM
Rule cost:   NONTERM
Rule guard:  (-1+ct_115^0 >= 0 /\ -ct_115^0+__const_256^0 == 0 /\ -2-cnt_29^0+cnt_34^0 >= 0)