NO Solver Timeout: 4 Global Timeout: 300 No parsing errors! Init Location: 0 Transitions: undef18, a33^0 -> 1, got_SIGHUP^0 -> 0, ret_XLogArchivingActive44^0 -> undef27, tmp2^0 -> undef30, tt1^0 -> (0 + undef30)}> 1}> undef132, a77^0 -> 0, curtime^0 -> (0 + undef141), ret_time88^0 -> undef141}> undef164, a55^0 -> 0, last_copy_time^0 -> (0 + undef172), ret_time66^0 -> undef172, wakend^0 -> 0}> undef243, got_SIGHUP^0 -> (0 + undef243), wakend^0 -> 1}> Fresh variables: undef18, undef27, undef30, undef132, undef141, undef164, undef172, undef243, undef257, Undef variables: undef18, undef27, undef30, undef132, undef141, undef164, undef172, undef243, undef257, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: (0 + undef172)}> (0 + undef172)}> (0 + undef172)}> (0 + undef172)}> Fresh variables: undef18, undef27, undef30, undef132, undef141, undef164, undef172, undef243, undef257, Undef variables: undef18, undef27, undef30, undef132, undef141, undef164, undef172, undef243, undef257, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: Variables: Precedence: Graph 0 Graph 1 undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 7 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.001214 > No variable changes in termination graph. Checking conditional unfeasibility... Termination failed. Trying to show unreachability... Proving unreachability of entry: undef172, rest remain the same}> LOG: CALL check - Post:1 <= 0 - Process 1 * Exit transition: undef172, rest remain the same}> * Postcondition : 1 <= 0 LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000296s > Postcondition is not implied! LOG: RETURN check - Elapsed time: 0.000348s Cannot prove unreachability Proving non-termination of subgraph 1 Transitions: Variables: Checking conditional non-termination of SCC {l7}... > No exit transition to close. Calling reachability with... Transition: Conditions: Transition: Conditions: Transition: Conditions: Transition: Conditions: Transition: Conditions: OPEN EXITS: --- Reachability graph --- > Graph without transitions. Calling reachability with... Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: undef172, rest remain the same}> Conditions: Transition: Conditions: OPEN EXITS: undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> undef172, rest remain the same}> > Conditions are reachable! Program does NOT terminate