YES

Solver Timeout: 4
Global Timeout: 300
No parsing errors!
Init Location: 0
Transitions:
<l0, l5, true>
<l1, l2, (10 <= (0 + i4^0))>
<l1, l3, ((1 + i4^0) <= 10), par{i4^0 -> (1 + i4^0)}>
<l3, l1, true>
<l4, l3, (undef8 = undef8), par{i4^0 -> 0, tmp^0 -> undef8}>
<l5, l4, true>

Fresh variables:
undef8, 

Undef variables:
undef8, 

Abstraction variables:

Exit nodes:

Accepting locations:

Asserts:

Preprocessed LLVMGraph
Init Location: 0
Transitions:
<l0, l3, (i4^0 = 0) /\ (undef8 = undef8)>
<l3, l2, (10 <= (0 + i4^0))>
<l3, l3, ((1 + i4^0) <= 10), par{i4^0 -> (1 + i4^0)}>

Fresh variables:
undef8, 

Undef variables:
undef8, 

Abstraction variables:

Exit nodes:

Accepting locations:

Asserts:

*************************************************************
*******************************************************************************************
***********************       WORKING TRANSITION SYSTEM (DAG)       ***********************
*******************************************************************************************

Init Location: 0
Graph 0:
Transitions:
Variables:

Graph 1:
Transitions:
<l3, l3, i4^0 <= 9, {i4^0 -> 1 + i4^0, rest remain the same}>
Variables:
i4^0

Graph 2:
Transitions:
Variables:

Precedence: 
Graph 0

Graph 1
<l0, l3, i4^0 = 0, {all remain the same}>

Graph 2
<l3, l2, 10 <= i4^0, {all remain the same}>

Map Locations to Subgraph:
( 0 , 0 )
( 2 , 2 )
( 3 , 1 )

*******************************************************************************************
********************************    CHECKING ASSERTIONS    ********************************
*******************************************************************************************

Proving termination of subgraph 0
Proving termination of subgraph 1
Checking unfeasibility...
Time used: 0.001368

Checking conditional termination of SCC {l3}...

LOG: CALL solveLinear

LOG: RETURN solveLinear - Elapsed time: 0.000532s
Ranking function: 9 - i4^0
New Graphs: 
Proving termination of subgraph 2
Analyzing SCC {l2}...
No cycles found.

Program Terminates